公开(公告)号：US08883655B2

公开(公告)日：2014-11-11

申请号：US13897050

申请日：2013-05-17

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L21/31 ,  H01L21/469 ,  H01L45/00 ,  H01L21/02 ,  C23C16/455 ,  C23C16/40 ,  H01L27/24

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US20140315369A1

公开(公告)日：2014-10-23

申请号：US14317155

申请日：2014-06-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。 这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。 其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压为至少约8V。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20140273427A1

公开(公告)日：2014-09-18

申请号：US14140807

申请日：2013-12-26

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L21/28

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract translation: 可以使用YBCO基导电材料作为电极，其可以与诸如高k电介质的电介质接触。 或者，具有窄导带的材料可以用作可以与诸如高k电介质的电介质接触的电极。 通过将电介质与YBCO基电极的带隙或窄带导电材料电极的带隙对准，例如，电介质的导带最小值落入基于YBCO的电极的带隙之一或 窄带导电材料可以减少通过电介质的热离子泄漏，因为电极中激发的电子或空穴需要较高的热激发能量以克服通过电介质层之前的带隙。

公开(公告)号：US20140268993A1

公开(公告)日：2014-09-18

申请号：US13838640

申请日：2013-03-15

Applicant: INTERMOLECULAR INC.

Inventor： Tony P. Chiang ,  Dipankar Pramanik ,  Milind Weling

IPC: G11C13/00

CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146

Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Abstract translation: 非易失性电阻性存储元件包括吸氧层。 吸氧层形成为电极堆叠的一部分，并且在吸电氧中比电极堆叠的其它层更热力学上更有利。 氧吸收层的氧化物的吉布斯自由能（＆Dgr; fG°）比形成电极堆叠的相邻层的氧化物的吉布斯自由能更少（即更负）。 吸氧层与存在于电极堆叠的相邻层中的氧气反应，从而防止这种氧扩散到附近的硅层中，从而不期望地增加存储元件中的SiO 2界面层厚度，并且可以选择以减少这种厚度 后续处理。

公开(公告)号：US20140264281A1

公开(公告)日：2014-09-18

申请号：US14137183

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Sandip Niyogi ,  Sean Barstow ,  Chi-I Lang ,  Ratsamee Limdulpaiboon ,  Dipankar Pramanik ,  J. Watanabe

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.

Abstract translation: 公开了半导体器件及其制造方法。 提供场效应晶体管（FET），其包括基板，设置在基板上方的第一层，第一层可操作为栅电极，第二层设置在第一层上方，第二层包括电介质材料，第三层 层，其设置在所述第二层上方，所述第三层包括半导体，以及包括一个或多个导电材料并可操作为设置在所述第三层上方的源极和漏极的第四层。 在一些实施例中，电介质材料包括高压 电介质。 在一些实施例中，源电极和漏电极包括一种或多种金属。 源电极和漏电极各自与第三层的顶表面的区域欧姆接触，并且基本上所有通过晶体管的电流都流经欧姆接触。

公开(公告)号：US20140264224A1

公开(公告)日：2014-09-18

申请号：US13969469

申请日：2013-08-16

Applicant: Intermolecular, Inc.

Inventor： Xuena Zhang ,  Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

Abstract translation: 电阻随机存取存储器（ReRAM）单元可以包括嵌入金属纳米颗粒切换层和电极。 可以使用胶束溶液形成金属纳米颗粒。 可以在多个维度上控制纳米颗粒的产生以实现期望的性能特征，例如低功耗以及低和一致的开关电流。

公开(公告)号：US20140224645A1

公开(公告)日：2014-08-14

申请号：US14254155

申请日：2014-04-16

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

IPC: H01L45/00

CPC classification number: C23C14/345 ,  C23C14/0042 ,  C23C14/0641 ,  C23C14/083 ,  C23C14/225 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ωcm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract translation: 公开了一种非易失性存储元件，其包括第一电极，具有双稳态电阻的近化学计量的金属氧化物存储层和与近化学计量的金属氧化物存储层接触的第二电极。 至少一个电极是包含亚化学计量的过渡金属氮化物或氧氮化物的电阻电极，并且电阻率在0.1和10Ω之间。 电阻电极提供嵌入式限流电阻器的功能，并且还用作用于设置和复位金属氧化物层的电阻状态的氧空位的源极和吸收器。 还公开了用于第二电极的新颖制造方法。

公开(公告)号：US20140191365A1

公开(公告)日：2014-07-10

申请号：US13738127

申请日：2013-01-10

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31122 ,  H01L28/91

Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.

Abstract translation: 方法包括从衬底上的第一材料形成电介质层。 电介质层形成为使得第一材料的至少一个电性能的优选晶体方向平行于电介质层的表面。 接下来，在电介质层内形成第一和第二沟槽，其中第一和第二沟槽具有至少一个弯曲部分。 在第一沟槽内形成第二材料，在第二沟槽内形成第三材料，其中第一材料与第二和第三材料不同。 第一和第二沟槽间隔3-20nm的距离。

公开(公告)号：US08766404B1

公开(公告)日：2014-07-01

申请号：US13738127

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/31122 ,  H01L28/91

Abstract: Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm.

Abstract translation: 方法包括从衬底上的第一材料形成电介质层。 电介质层形成为使得第一材料的至少一个电性能的优选晶体方向平行于电介质层的表面。 接下来，在电介质层内形成第一和第二沟槽，其中第一和第二沟槽具有至少一个弯曲部分。 在第一沟槽内形成第二材料，在第二沟槽内形成第三材料，其中第一材料与第二和第三材料不同。 第一和第二沟槽间隔3-20nm的距离。

公开(公告)号：US20140177315A1

公开(公告)日：2014-06-26

申请号：US13721279

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Dipankar Pramanik ,  David E. Lazovsky ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C11/56 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/145 ,  H01L45/1608

Abstract: A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Abstract translation: 提供了用于多位数据存储的电阻器阵列，而不需要增加存储器芯片的尺寸或缩小存储器芯片中包含的存储器单元的特征尺寸。 电阻器阵列包括多个离散电阻元件，以便以不同的串联组合方式连接到至少一个存储器单元或存储器件。 在一种配置中，通过将每个存储器单元或设备连接至少一个电阻器阵列，在连接的存储器件的电阻式开关存储器元件中发现的电阻式开关层能够处于多个电阻状态，用于存储多位数字信息。 在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，连接的存储器件中的电阻式开关层可以处于期望的电阻状态。