公开(公告)号：US10290682B2

公开(公告)日：2019-05-14

申请号：US15803732

申请日：2017-11-03

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L29/06 ,  H01L47/00 ,  H01L27/24 ,  H01L27/108 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11 ,  H01L27/06 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  H01L21/683 ,  H01L21/268 ,  H01L27/22 ,  H01L29/423 ,  H01L45/00 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/105

Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.

公开(公告)号：US20190074371A1

公开(公告)日：2019-03-07

申请号：US16174152

申请日：2018-10-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/78

Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a first silicon channel; a second layer including second transistors each including a second silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer overlying the second transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistors are junction-less transistors.

公开(公告)号：US10217667B2

公开(公告)日：2019-02-26

申请号：US15904347

申请日：2018-02-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/822 ,  H01L25/065 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  G11C17/14 ,  H01L21/8238 ,  H01L27/11 ,  H01L23/00 ,  H01L23/48

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

公开(公告)号：US20190006222A1

公开(公告)日：2019-01-03

申请号：US16101489

申请日：2018-08-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L21/683 ,  H01L29/792 ,  G11C8/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11526 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/10 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L23/525 ,  H01L23/48 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/768 ,  H01L21/762 ,  H01L21/74 ,  H01L29/788 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

Abstract: A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

公开(公告)号：US09953925B2

公开(公告)日：2018-04-24

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/544 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/10 ,  H01L21/84 ,  H01L21/683 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C11/41 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L23/00 ,  H01L29/66 ,  H01L27/088 ,  H01L23/36

CPC classification number: H01L23/5286 ,  B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/36 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

公开(公告)号：US09892972B2

公开(公告)日：2018-02-13

申请号：US15201430

申请日：2016-07-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L45/00 ,  H01L27/115 ,  H01L27/06 ,  H01L27/088 ,  H01L27/24 ,  H01L27/11 ,  H01L27/108 ,  H01L23/367 ,  H01L27/22 ,  H01L21/762 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/085 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L23/367 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/226 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/42392 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.

公开(公告)号：US09818800B2

公开(公告)日：2017-11-14

申请号：US14555494

申请日：2014-11-26

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L29/06 ,  H01L27/118 ,  H01L27/24 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L27/22 ,  H01L29/78 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11573 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

公开(公告)号：US20170229174A1

公开(公告)日：2017-08-10

申请号：US15494525

申请日：2017-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G11C13/00 ,  H01L45/00 ,  H01L29/04 ,  G11C29/00 ,  H01L27/24 ,  H01L29/161

CPC classification number: G11C13/0069 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C16/0483 ,  G11C29/78 ,  G11C2013/0076 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

公开(公告)号：US09691869B2

公开(公告)日：2017-06-27

申请号：US14880276

申请日：2015-10-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00 ,  H01L29/45 ,  H01L29/66 ,  H01L23/544 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/456 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66704 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

公开(公告)号：US20170179155A1

公开(公告)日：2017-06-22

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/11582 ,  H01L45/00 ,  H01L27/108

CPC classification number: H01L45/1206 ,  H01L21/76254 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.