公开(公告)号：US5284548A

公开(公告)日：1994-02-08

申请号：US25550

申请日：1993-03-03

Applicant: David H. Carey ,  David J. Burger

Inventor： David H. Carey ,  David J. Burger

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  C23F1/00

CPC classification number: H05K3/4626 ,  H05K3/108 ,  H05K3/427 ,  H05K3/4655 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09581 ,  H05K2203/072 ,  H05K2203/1407 ,  H05K3/064 ,  H05K3/386 ,  H05K3/388 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4652

Abstract: A process for producing fine pitch surface features on a multilayer printed circuit boards such as copper-polyimide interconnects without requiring a thick copper plating foil. Initially, a thin first conductor (less than 1 micron) is vacuum deposited on a dielectric base and the dielectric base is disposed on a substrate. The substrate is then laminated and through-holes are formed therethrough. A plating seed is deposited in the through-holes and resist is patterned on the first conductor. A second conductor is deposited on the exposed portions of the first conductor and on the sidewalls, the resist is stripped and the portions or the first conductor beneath the resist are removed using a brief wet chemical etch to form spaced features without significant undercut. In the preferred embodiment, vacuum deposition occurs in a continuous roll sputtering system.

Abstract translation: 在多层印刷电路板（例如铜 - 聚酰亚胺互连）上生产细间距表面特征的方法，而不需要厚的镀铜箔。 首先，将薄的第一导体（小于1微米）真空沉积在电介质基底上，并将电介质基底设置在基底上。 然后层压基板，并且通过其形成通孔。 电镀种子沉积在通孔中，抗蚀剂被图案化在第一导体上。 第二导体沉积在第一导体的暴露部分上并且在侧壁上，剥离抗蚀剂，并且使用短暂的湿化学蚀刻去除抗蚀剂下面的部分或第一导体，以形成间隔的特征而没有显着的底切。 在优选实施例中，在连续辊式溅射系统中发生真空沉积。

公开(公告)号：US5272600A

公开(公告)日：1993-12-21

申请号：US939228

申请日：1992-09-02

Applicant: David H. Carey

Inventor： David H. Carey

IPC: H01L23/538 ,  H01L23/64 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16 ,  H05K1/14

CPC classification number: H05K1/162 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K1/115 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09345

Abstract: The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

Abstract translation: 本发明涉及一种具有电源和地线的电互连装置，其中信号线层和信号层之间的电容通孔交织在一起，以便有效地利用信号线和信号层之间的未被接合的区域，并减少或消除对分离电力的需要 和接地层，同时在布线结构内提供去耦电容。

公开(公告)号：US5265321A

公开(公告)日：1993-11-30

申请号：US949182

申请日：1992-09-22

Applicant: Richard D. Nelson ,  Michael A. Olla ,  Seyed H. Hashemi ,  Thomas P. Dolbear

Inventor： Richard D. Nelson ,  Michael A. Olla ,  Seyed H. Hashemi ,  Thomas P. Dolbear

IPC: H01L23/367 ,  H01L23/433 ,  H05K7/20

CPC classification number: H01L23/4334 ,  H01L23/3677 ,  H01L23/4338 ,  H01L2924/0002 ,  Y10T29/49146 ,  Y10T29/4981

Abstract: An integrated circuit structure and method of making in which the circuit has a plurality of metal heat exchanger elements spaced from each other with their first ends secured to the structure. The first ends may be adhesively secured to an integrated circuit chip or the underlying substrate, and the heat exchanger may be hermetically attached. The method uses a compliant removable support block for attaching the plurality of individual heat exchanger elements to integrated circuit structures having variations in their elevation.

Abstract translation: 一种集成电路结构和制造方法，其中电路具有彼此间隔开的多个金属热交换器元件，其第一端固定到结构。 第一端可以粘合地固定到集成电路芯片或下面的基板，并且热交换器可以气密地附接。 该方法使用柔性可移除的支撑块，用于将多个单独的热交换器元件连接到具有其高度变化的集成电路结构。

公开(公告)号：US5250329A

公开(公告)日：1993-10-05

申请号：US976057

申请日：1992-11-13

Applicant: Robert Miracky ,  Joan E. Yater ,  Colin A. Mackay

Inventor： Robert Miracky ,  Joan E. Yater ,  Colin A. Mackay

IPC: C23C16/04 ,  H01L21/3205 ,  H05K3/14 ,  B05D3/06 ,  C23C14/00 ,  C23C16/00 ,  H01L21/306

CPC classification number: H01L21/32051 ,  C23C16/047 ,  H05K3/146

Abstract: A method of depositing micron-sized metal lines on a dielectric substrate, such as polyimide. The dielectric is covered with a thin metallic layer, of a first metal placed in a reaction cell containing a gas-phase molecular species containing a second metal, and exposed to a focused laser beam. A translation stage moves the dielectric relative to the beam to selectively deposit micron-sized second metal lines on the metallic layer. The metallic layer on the unirradiated portion of the substrate is subsequently etched away, leaving the lines adhered to the dielectric surface.

Abstract translation: 将微米尺寸金属线沉积在诸如聚酰亚胺的电介质基底上的方法。 电介质覆盖有薄金属层，第一金属放置在含有含有第二金属的气相分子物质并暴露于聚焦激光束的反应池中。 平移台相对于光束移动电介质以选择性地在金属层上沉积微米级的第二金属线。 随后将衬底的未照射部分上的金属层蚀刻掉，使线粘附到电介质表面。

公开(公告)号：US5244538A

公开(公告)日：1993-09-14

申请号：US736357

申请日：1991-07-26

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H05K3/045 ,  H05K3/184 ,  H05K3/465 ,  H01J2201/30457 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0376 ,  H05K2201/2081 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/1338 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/143 ,  H05K3/146 ,  H05K3/185 ,  H05K3/388 ,  H05K3/4661

Abstract: A method of patterning metal on a substrate without photolithography. The steps include providing a dielectric substrate, forming a metal mask in a predetermined pattern on the substrate without using a mask by direct-write deposition using a particle beam such as a liquid metal cluster force to form the mask, dry etching the substrate to form a plurality of channels therein, depositing a conductive metal into the channels, and removing the mask. The top of the substrate can then be planarized by polishing, or alternatively the dielectric between the metal lines can be etched. The invention is well suited for fabricating copper/polyimide substrates.

Abstract translation: 在没有光刻的基板上图案化金属的方法。 所述步骤包括提供电介质基板，在基板上以预定图案形成金属掩模，而不用使用诸如液体金属簇力的粒子束的直接写入沉积来形成掩模，干燥蚀刻基板以形成 多个通道，将导电金属沉积到通道中，以及去除掩模。 然后可以通过抛光将衬底的顶部平坦化，或者可以蚀刻金属线之间的电介质。 本发明非常适用于制造铜/聚酰亚胺基片。

公开(公告)号：US5236551A

公开(公告)日：1993-08-17

申请号：US972665

申请日：1992-11-06

Applicant: Ju-Don T. Pan

Inventor： Ju-Don T. Pan

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H05K3/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/46

CPC classification number: H05K3/225 ,  H01L21/485 ,  H01L21/76802 ,  H01L21/76894 ,  H01L23/49866 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/0195 ,  H05K2203/0769 ,  H05K2203/107 ,  H05K2203/175 ,  H05K3/0017 ,  H05K3/06 ,  H05K3/061 ,  H05K3/4644 ,  Y10S438/94

Abstract: A metal/polymeric dielectric substrate has metal conductors selectively disconnected by photoablating the polymeric dielectric with an excimer laser, etching the exposed metal using the polymeric dielectric as a mask, and coating an additional layer of polymeric dielectric. This eliminates the need for depositing and removing a separate photoablatable mask. Siloxane-modified-polyimide is a preferred photoablatable polymeric material and copper is a preferred metal.

Abstract translation: 金属/聚合物电介质衬底通过用准分子激光器照射聚合物电介质来选择性地断开金属导体，使用聚合物电介质作为掩模蚀刻暴露的金属，以及涂覆另外的聚合物电介质层。 这消除了沉积和移除单独的可光化掩模的需要。 硅氧烷改性聚酰亚胺是优选的可光化聚合材料，铜是优选的金属。

公开(公告)号：US5224022A

公开(公告)日：1993-06-29

申请号：US524237

申请日：1990-05-15

Applicant: William Weigler ,  Gregory E. Pitts

Inventor： William Weigler ,  Gregory E. Pitts

IPC: H01L23/538 ,  H05K1/00

CPC classification number: H01L23/5386 ,  H01L23/5382 ,  H05K1/0289 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0292

Abstract: A multilayered electrical interconnect circuit whereby interconnect lines, placed in channel regions throughout a rerouting substrate, function to reroute densely packaged electrical components via geometrically uniform spot links placed upon only the surface layer within each channel region. The interconnect circuit has closely spaced parallel X-and Y-lines orthogonal to one another, each X- and Y-line placed within horizontal and vertical channel regions, respectively, such that electrical connections between closely spaced large-scale integrated circuits or discrete electrical components can be rerouted with a combination of one or more X- and/or Y-lines.

Abstract translation: 一种多层电互连电路，由此布置在遍布整个路由衬底的通道区域中的互连线用于通过仅放置在每个沟道区域内的表面层上的几何均匀的点连接来重新路由密集封装的电气部件。 互连电路具有彼此正交的紧密间隔的平行X线和Y线，每个X线和Y线分别放置在水平和垂直通道区域内，使得紧密间隔的大规模集成电路或分立电路 组件可以通过一个或多个X和/或Y线的组合重新路由。

公开(公告)号：US5199918A

公开(公告)日：1993-04-06

申请号：US789237

申请日：1991-11-07

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01J1/304 ,  H01J9/02

CPC classification number: H01J1/3042 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30457

Abstract: A field emitter device comprising a conductive metal and a diamond emission tip with negative electron affinity in ohmic contact with and protruding above the metal. The device is fabricated by coating a substrate with an insulating diamond film having negative electron affinity and a top surface with spikes and valleys, depositing a conductive metal on the diamond film, and applying an etch to expose the spikes without exposing the valleys, thereby forming diamond emission tips which protrude a height above the conductive metal less than the mean free path of electrons in the diamond film.

Abstract translation: 一种场致发射器件，包括导电金属和具有负电子亲和力的金刚石发射尖端，与金属欧姆接触并突出在金属上方。 该器件通过用具有负电子亲和性的绝缘金刚石膜和具有尖峰和谷的顶表面的衬底涂覆衬底，在金刚石膜上沉积导电金属，以及施加蚀刻以暴露尖峰而不暴露谷，从而形成 金刚石发射尖端突出高于导电金属的高度小于金刚石膜中电子的平均自由程。

公开(公告)号：US5192913A

公开(公告)日：1993-03-09

申请号：US851716

申请日：1992-03-16

Applicant: Rama R. Goruganthu ,  Thomas K. Myers ,  Andrew W. Ross

Inventor： Rama R. Goruganthu ,  Thomas K. Myers ,  Andrew W. Ross

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/305

CPC classification number: G01R31/025 ,  G01R31/2853 ,  G01R31/305

Abstract: A method of electrically testing an electrical component containing a plurality of networks with at least one node. The method uses segmented, charge limiting testing to charge the nodes and detect shorted or disconnected nodes while preventing accumulated charges in the networks from making uncharged nodes appear charged. The method is well suited for voltage contrast electron beam testing of unpopulated high density multichip modules and interconnect substrates.

Abstract translation: 一种用至少一个节点电测试包含多个网络的电气部件的方法。 该方法使用分段的电荷限制测试来对节点进行充电并检测短路或断开的节点，同时防止网络中的累积电荷使得不带电节点出现充电。 该方法非常适用于未填充的高密度多芯片模块和互连衬底的电压对比电子束测试。

公开(公告)号：US5187671A

公开(公告)日：1993-02-16

申请号：US572744

申请日：1990-08-24

Applicant: Deborah D. Cobb

Inventor： Deborah D. Cobb

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method of manufacturing a multiple element circuit interconnect substrate is provided which provides an optimized routing plan. The routing plan is based upon a multi-dimensional binary data structure having nodes representing each terminal interconnect requirement which is preprocessed to order the required interconnects according to density.

Abstract translation: 提供一种制造多元件电路互连基板的方法，其提供优化的布线方案。 该路由计划基于具有表示每个终端互连需求的节点的多维二进制数据结构，其中该终端互连需求被预处理以根据密度对所需的互连进行排序。