公开(公告)号：US09768147B2

公开(公告)日：2017-09-19

申请号：US14171169

申请日：2014-02-03

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L29/06 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US09733304B2

公开(公告)日：2017-08-15

申请号：US14495025

申请日：2014-09-24

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US09704781B2

公开(公告)日：2017-07-11

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/498 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US09449940B2

公开(公告)日：2016-09-20

申请号：US14569272

申请日：2014-12-12

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L24/50 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12042 ,  H01L2924/00012

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate. Structures include a polymeric material comprising Si—O—Si disposed over a first substrate, an adhesive material disposed over the first substrate and at least a portion of the polymeric material, and a second substrate disposed over the adhesive material.

Abstract translation: 形成半导体结构的方法包括将载体衬底暴露于硅烷材料以形成涂层，至少邻近载体衬底的周边移除涂层的一部分，将另一衬底粘合到载体衬底上，并分离另一衬底 从载体衬底。 硅烷材料包括具有（XO）3 Si（CH 2）n Y，（XO）2 Si（（CH 2）n Y）2或（XO）3 Si（CH 2）n Y（CH 2）n Si（XO）3的结构的化合物，其中 XO是可水解的烷氧基，Y是有机官能团，n是非负整数。 一些方法包括在第一衬底上形成包含Si-O-Si的聚合材料，去除聚合物材料的一部分，并将另一衬底粘合到第一衬底上。 结构包括设置在第一衬底上的Si-O-Si的聚合物材料，设置在第一衬底上的粘合剂材料和聚合物材料的至少一部分，以及设置在粘合剂材料上的第二衬底。

公开(公告)号：US09443744B2

公开(公告)日：2016-09-13

申请号：US14330934

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/04 ,  H01L21/50 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。

公开(公告)号：US20160084905A1

公开(公告)日：2016-03-24

申请号：US14495025

申请日：2014-09-24

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC: G01R31/28 ,  G01R1/073 ,  G01R1/04

CPC classification number: G01R31/2887 ,  G01R1/07307 ,  G01R31/2884

Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

Abstract translation: 用于测试包括管芯堆叠的半导体器件的设备，该设备包括其表面中具有凹穴阵列的衬底，其布置成对应于从待测试的半导体器件突出的导电元件。 凹穴包括导电接触件，导线延伸到导电焊盘，其可被配置为测试焊盘，跳线焊盘，边缘连接或接触焊盘。 衬底可以包括半导体晶片或晶片段，并且如果后者，多个段可以被容纳在固定装置中的凹槽中。 可以使用探针卡，承载导电针的接合头或通过固定器承载的导体进行测试。

公开(公告)号：US20160013115A1

公开(公告)日：2016-01-14

申请号：US14330934

申请日：2014-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/34 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。

公开(公告)号：US09224715B2

公开(公告)日：2015-12-29

申请号：US14625325

申请日：2015-02-18

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11824 ,  H01L2224/11848 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81355 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/3651 ,  H01L2924/00012 ,  H01L2924/01016 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material.

Abstract translation: 公开了半导体组件，结构和制造方法。 在导电柱上形成涂层。 可以由硅烷材料和有机可焊性保护剂材料中的至少一种形成的涂层可以结合到导电柱的导电材料和任选地粘合到导电柱的其它金属材料。 涂层还可以结合到基底钝化材料（如果存在）上，或者粘合到基底和接合垫的其它暴露表面。 可以在导电材料上选择性地形成涂层。 在其形成之后并且在用于管芯附着的焊料的回流之前，材料可能不会从涂层中去除。 涂层可以至少将导电材料与焊料隔离开来，阻止焊料芯吸或沿导电材料塌陷，并且可以增强所得到的粘合的导电元件和底部填充材料之间的粘附。

公开(公告)号：US20150137353A1

公开(公告)日：2015-05-21

申请号：US14084037

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

Abstract translation: 本技术涉及制造具有用于管芯到管芯和/或封装到封装互连或其它类型互连的具有凸块下金属（UBM）结构的半导体管芯。 在一个实施例中，用于在半导体管芯上形成凸块状凸起的金属（UBM）结构的方法包括通过将第一材料镀在种子结构的第一区域上并在第一材料上沉积第二材料来构造UBM柱。 第一材料具有第一电位，第二材料具有大于第一电位的第二电势。 该方法还包括减小第一材料和第二材料之间的电位差，然后去除UBM柱之间的种子结构的第二区域，从而在半导体管芯上形成UBM结构。

公开(公告)号：US09034769B2

公开(公告)日：2015-05-19

申请号：US13712699

申请日：2012-12-12

Applicant: Micron Technology, Inc.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L21/302 ,  H01L21/461 ,  H01L23/538 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损害填充通孔的铜，并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。