公开(公告)号：US20190019538A1

公开(公告)日：2019-01-17

申请号：US15817441

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

CPC classification number: G11C5/02 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/161 ,  G11C11/223 ,  G11C11/54 ,  G11C13/0002 ,  G11C16/0483 ,  H03K19/18

Abstract: Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

公开(公告)号：US20180259581A1

公开(公告)日：2018-09-13

申请号：US15455253

申请日：2017-03-10

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Yang Du

IPC: G01R31/3185 ,  H01L21/66 ,  H01L27/06 ,  H01L23/528 ,  H01L23/34 ,  H03K3/03 ,  H03K17/14

CPC classification number: G01R31/318513 ,  G01R31/318505 ,  H01L22/34 ,  H01L23/34 ,  H01L23/5286 ,  H01L25/0657 ,  H01L27/0688 ,  H03K3/0315 ,  H03K17/14

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.

公开(公告)号：US09601617B2

公开(公告)日：2017-03-21

申请号：US14604544

申请日：2015-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Xia Li ,  Bin Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

公开(公告)号：US09548096B1

公开(公告)日：2017-01-17

申请号：US14835871

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

Abstract translation: 公开了采用共享源线的反向补码MTJ比特单元。 在一个方面，提供了采用共享源线的2T2MTJ反向补码位单元。 位单元包括第一MTJ和第二MTJ。 第一MTJ的价值是第二MTJ的价值的补充。 第一位线耦合到第一MTJ的顶层，第一存取晶体管的第一电极耦合到第一MTJ的底层。 第二位线耦合到第二MTJ的底层，第二存取晶体管的第一电极耦合到第二MTJ的顶层。 字线耦合到第一存取晶体管和第二存取晶体管的第二电极。 共享源极线耦合到第一存取晶体管和第二存取晶体管的第三电极。 采用共享源极线允许位单元被设计成具有减小的寄生电阻。

公开(公告)号：US09508439B2

公开(公告)日：2016-11-29

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  G11C16/26 ,  H01L27/112

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US09502424B2

公开(公告)日：2016-11-22

申请号：US13684107

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L27/112 ,  H01L21/8239 ,  G11C17/16 ,  H01L23/522 ,  H01L23/525 ,  H01L49/02 ,  H01L27/105

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

公开(公告)号：US09385305B2

公开(公告)日：2016-07-05

申请号：US13770306

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： William H. Xia ,  Wenqing Wu ,  Kendrick H. Yuen ,  Abhishek Banerjee ,  Xia Li ,  Seung H. Kang ,  Jung Pill Kim

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract translation: 存储单元包括耦合到磁隧道结（MTJ）结构的细长第一电极和与耦合到MTJ结构的细长第一电极对准的细长第二电极。 细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。 响应于开关电流的应用，相互添加的部分增强MTJ的切换。

公开(公告)号：US09373782B2

公开(公告)日：2016-06-21

申请号：US14518459

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Matthew Michael Nowak

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract translation: 存储器件可以包括磁性隧道结（MTJ）堆叠，底部电极（BE）层和接触层。 MTJ堆叠可以包括自由层，阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠，并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中，并且在BE层和MTJ堆叠之间形成界面。

公开(公告)号：US20160012896A1

公开(公告)日：2016-01-14

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  G11C16/26 ,  H01L29/51

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US09236483B2

公开(公告)日：2016-01-12

申请号：US14179311

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Pr Chidambaram ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/66 ,  H03K17/687

CPC classification number: H01L29/7855 ,  H01L29/0607 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H03K17/687 ,  H03K2017/6878 ,  H03K2217/0018 ,  H03K2217/0054

Abstract: A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.

Abstract translation: 在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。 阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。 后门提供改进的电流控制。 由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。