公开(公告)号：US5917477A

公开(公告)日：1999-06-29

申请号：US807683

申请日：1997-02-28

Applicant: Jong-ho Lee

Inventor： Jong-ho Lee

IPC: B25J9/22 ,  B25J9/06 ,  G05B19/409 ,  G06F3/041 ,  G06F3/14 ,  G09G5/00

CPC classification number: G05B19/409 ,  G06F3/0416 ,  G05B2219/32266 ,  G05B2219/36153 ,  G05B2219/36168 ,  G05B2219/45026 ,  G06F3/1423 ,  Y02P90/20

Abstract: A touch screen input apparatus including a plurality of touch screens, a chip mounter provided with the apparatus, and a method for controlling the chip mounter are provided which improve the capability of controlling the chip mounter. The touch screen input apparatus of a chip mounter comprises a plurality of monitors dispersedly disposed in the vicinity of the chip mounter to provide display screens for inputting the letter or numeral, a touch panel attached to each monitor for recognizing a touched coordinate on each display screen and outputting an electrical signal, priority order and release time controlling means for receiving the signals output from the touch panels and recognizing the order of generation thereof, and a multiplexer for receiving the signals output from the touch panels and sequentially selecting and outputting the input signals according to the order recognized by the priority order and release time controlling means. The touch screen input apparatus includes the monitors and the touch screen which are located at different places in order to control the chip mounter, thereby improving the operational capability of the chip mounter.

Abstract translation: 提供了包括多个触摸屏的触摸屏输入装置，设置有该装置的芯片安装机和用于控制芯片安装机的方法，其提高了控制芯片安装机的能力。 芯片安装器的触摸屏输入装置包括分散地设置在芯片安装机附近的多个监视器，以提供用于输入字母或数字的显示屏幕，附接到每个监视器的触摸面板，用于识别每个显示屏幕上的触摸坐标 并且输出电信号，优先顺序和释放时间控制装置，用于接收从触摸面板输出的信号并识别其生成顺序;以及多路复用器，用于接收从触摸面板输出的信号，并顺序选择并输出输入信号 根据优先顺序确认的顺序和释放时间控制手段。 触摸屏输入装置包括位于不同位置的监视器和触摸屏，以便控制芯片安装器，从而提高贴片机的操作能力。

公开(公告)号：US5837494A

公开(公告)日：1998-11-17

申请号：US860529

申请日：1997-06-30

Applicant: Jong Ho Lee ,  Han Choi ,  Il Lae Jung ,  Doe Sun Na ,  Young Min Park

Inventor： Jong Ho Lee ,  Han Choi ,  Il Lae Jung ,  Doe Sun Na ,  Young Min Park

IPC: C12N15/00 ,  C07K14/47 ,  C12N1/20 ,  C12N1/21 ,  C12N15/12 ,  C12N15/70 ,  C12P21/02 ,  C12R1/19 ,  C12P21/06

CPC classification number: C07K14/4721 ,  C12N15/70 ,  C12R1/19 ,  Y10S435/849

Abstract: Disclosed herein is a new E. coli mutant, which is not capable of growing under anaerobic cultivation conditions, said mutant being capable of utilizing glucose as a carbon source but having a suppressed organic acid production under aerobic cultivation conditions. The mutant can advantageously be employed as an expression host system to produce recombinant proteins.

Abstract translation: PCT No.PCT / KR96 / 00186 Sec。 371日期：1997年6月30日 102（e）日期1996年6月30日PCT提交1996年10月29日PCT公布。 公开号WO97 / 16530 日期1997年5月9日这里公开的是一种新的大肠杆菌突变体，其不能在厌氧培养条件下生长，所述突变体能够利用葡萄糖作为碳源，但在需氧培养条件下具有抑制的有机酸产生。 该突变体可有利地用作表达宿主系统以产生重组蛋白。

公开(公告)号：USD992700S1

公开(公告)日：2023-07-18

申请号：US29790393

申请日：2021-11-24

Applicant: Jong Ho Lee ,  Hye Jung Lee

Designer： Jong Ho Lee ,  Hye Jung Lee

Abstract: FIG. 1 is a perspective view of a pipe connecting tube showing our new design,
FIG. 2 is a front view thereof,
FIG. 3 is a rear view thereof,
FIG. 4 is a left-side view thereof,
FIG. 5 is a right-side view thereof,
FIG. 6 is a plan view thereof,
FIG. 7 is a bottom view thereof; and,
FIG. 8 is an exploded perspective view of thereof.
The light lines in the drawing figures depict transparent portions of the pipe connecting tube.
The present design is a pipe connecting tube used to connect pipes.
The broken lines shown in the figures are for the purpose of illustrating portions of the pipe connecting tube and form no part of the claimed design.

公开(公告)号：US20180221112A1

公开(公告)日：2018-08-09

申请号：US15946984

申请日：2018-04-06

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: A61C7/22

CPC classification number: A61C7/22 ,  A61C7/20 ,  A61C7/28

Abstract: Disclosed is an archwire with a varied cross section which is formed integrally with a hook. The archwire includes a customized archwire body corresponding to a setup model of patient's teeth, and the hook which is formed integrally with the archwire body. The archwire body is formed in such a way that at least one region has a cross section different from that of another region.

公开(公告)号：US08922012B2

公开(公告)日：2014-12-30

申请号：US12894540

申请日：2010-09-30

Applicant: Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

Inventor： Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/06 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

Abstract translation: 在集成电路（IC）芯片和具有其的倒装芯片封装中，不设置布线，并且第一电极焊盘不与IC芯片的焊盘区域中的布线接触。 因此，与焊盘区域中的布线无关，第一凸块结构与第一电极接触。 第二电极焊盘与IC芯片的伪焊盘区域中的布线接触。 因此，伪焊盘区域中的第二凸块结构在与第二电极下方的布线间隔开的接触点处与第二电极的上表面接触。

公开(公告)号：US08825262B2

公开(公告)日：2014-09-02

申请号：US13488705

申请日：2012-06-05

Applicant: Jong Ho Lee ,  Jae Hwan Jeon

Inventor： Jong Ho Lee ,  Jae Hwan Jeon

IPC: G01C22/00 ,  G05D1/00 ,  B62D15/02 ,  B60R1/00

CPC classification number: B62D15/027 ,  B60R1/00 ,  B62D15/0275 ,  B62D15/0285

Abstract: Disclosed herein is a technique of deriving a parking trajectory for a vehicle. In the technique, a first extension straight line, which includes a linear travel path of the vehicle when the vehicle initially goes in reverse from a neutral position of a steering angle, is calculated upon the vehicle being to go in reverse. A final parking location is obtained based on a calculated length of a parking space and a parking target location in the parking space, and a second extension straight line which includes the final parking location is calculated therefrom. When the vehicle going in reverse along the first extension straight line turns and goes in reverse towards the second extension straight line, an intermediate extension straight line connecting the first extension straight line and the second extension straight line is calculated so that the vehicle is aligned with the second extension straight line.

Abstract translation: 本文公开了一种导出车辆停车轨迹的技术。 在该技术中，当车辆反转时，计算当车辆最初从转向角的中立位置反向转动时包括车辆的线性行进路径的第一延伸直线。 基于计算停车空间的长度和驻车空间中的停车目标位置获得最终停车位置，并计算包括最终停车位置的第二延伸直线。 当车辆沿着第一延伸直线反向转动并朝向第二延伸直线反转时，计算连接第一延伸直线和第二延伸直线的中间延伸直线，使得车辆与 第二条直线延伸。

公开(公告)号：US20140198528A1

公开(公告)日：2014-07-17

申请号：US14239100

申请日：2011-08-17

Applicant: Yong Tae KIim ,  Tomio Inoue ,  Je Won Kim ,  Tsuyoshi Tsutsui ,  Jong Ho Lee ,  Seung Wan Chae

Inventor： Yong Tae KIim ,  Tomio Inoue ,  Je Won Kim ,  Tsuyoshi Tsutsui ,  Jong Ho Lee ,  Seung Wan Chae

IPC: H01L33/50 ,  F21V8/00

CPC classification number: G02B6/0073 ,  H01L33/486 ,  H01L33/505 ,  H01L2924/0002 ,  H01L2933/0041 ,  H01L2933/005 ,  H01L2933/0066 ,  H01L2924/00

Abstract: There is provided a method of manufacturing a wavelength converted LED chip, including attaching a plurality of LED chips to a chip alignment region of an upper surface of a temporary support plate, forming a conductive bump on the electrode of the respective LED chips, forming a phosphor-containing resin encapsulation part in the chip alignment region to cover the conductive bump, polishing the phosphor containing resin encapsulation part, forming the wavelength converted LED chips by cutting the provided phosphor containing resin encapsulation part between the LED chips, the wavelength converted LED chip including a wavelength conversion layer obtained from the phosphor containing resin encapsulation part and formed on lateral surfaces and an upper surface of the wavelength converted LED chip, and removing the temporary support plate from the wavelength converted LED chip.

Abstract translation: 提供一种制造波长转换LED芯片的方法，包括将多个LED芯片附接到临时支撑板的上表面的芯片对准区域，在各个LED芯片的电极上形成导电凸块，形成 含磷光体的树脂封装部分在芯片取向区域中覆盖导电凸块，抛光含荧光体的树脂封装部分，通过在LED芯片之间切割提供的含磷树脂封装部分，形成波长转换的LED芯片，波长转换的LED芯片 包括由含荧光体的树脂封装部分形成的波长转换层，并形成在波长转换的LED芯片的侧面和上表面上，并从波长转换的LED芯片上去除临时支撑板。

公开(公告)号：US20140183589A1

公开(公告)日：2014-07-03

申请号：US14237515

申请日：2011-08-09

Applicant: Jae Ho Han ,  Sung Tae Kim ,  Seung Wan Chae ,  Jong Ho Lee ,  Je Won Kim

Inventor： Jae Ho Han ,  Sung Tae Kim ,  Seung Wan Chae ,  Jong Ho Lee ,  Je Won Kim

IPC: H01L33/00 ,  H01L33/60

CPC classification number: H01L33/005 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L33/0095 ,  H01L33/46 ,  H01L33/60

Abstract: There are provided a method of manufacturing a semiconductor light emitting device and a semiconductor light emitting device manufactured thereby. According to an exemplary embodiment, a method of manufacturing a semiconductor light emitting device includes: forming a light emitting structure by sequentially growing a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer on a first main surface of a substrate, the substrate having first and second main surfaces opposing one another; forming a reflective film on the second main surface of the substrate, the reflective film including at least one laser absorption region; and performing a scribing process separating the light emitting structure and the substrate into device units by irradiating a laser from a portion of a top of the light emitting structure corresponding to the laser absorption region to the light emitting structure and the substrate.

Abstract translation: 提供一种制造半导体发光器件和由此制造的半导体发光器件的方法。 根据示例性实施例，制造半导体发光器件的方法包括：通过在衬底的第一主表面上依次生长第一导电类型半导体层，有源层和第二导电类型半导体层来形成发光结构 所述基板具有彼此相对的第一和第二主表面; 在所述基板的所述第二主表面上形成反射膜，所述反射膜包括至少一个激光吸收区域; 以及通过从对应于所述激光吸收区域的所述发光结构的顶部的一部分照射激光而将所述发光结构和所述衬底分离成器件单元的划线处理到所述发光结构和所述衬底。

公开(公告)号：US20130242460A1

公开(公告)日：2013-09-19

申请号：US13491192

申请日：2012-06-07

Applicant: Jong Ho LEE ,  Sung Chul Bae ,  Jae Yeol Choi ,  Sung Woo Kim ,  Yu Na Kim

Inventor： Jong Ho LEE ,  Sung Chul Bae ,  Jae Yeol Choi ,  Sung Woo Kim ,  Yu Na Kim

IPC: H01G4/005 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/0085 ,  H01G4/012 ,  H01G4/12

Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same, the multilayer ceramic electronic including: a ceramic body; and a plurality of internal electrodes laminated within the ceramic body, wherein, when T1 is the greatest distance between an upper outermost internal electrode and a lower outermost internal electrode among the plurality of internal electrodes and T2 is the distance between the highest point and the lowest point in each of the upper outermost internal electrode and the lower outermost internal electrode in a thickness direction of the ceramic body, T2/T1

Abstract translation: 提供了一种多层陶瓷电子部件及其制造方法，所述多层陶瓷电子器件包括：陶瓷体; 以及层叠在所述陶瓷体内的多个内部电极，其中，当所述多个内部电极中的最外侧内部电极与最外侧内部电极之间的距离为T1时，T2为最高点与最低点之间的距离 在陶瓷体的厚度方向上的最外侧内部电极和下部最外侧的内部电极中的每一个点都满足T2 / T1 <0.05，因此可能抑制多层陶瓷电子部件的内部电极的排列缺陷 。

公开(公告)号：US20130234287A1

公开(公告)日：2013-09-12

申请号：US13463334

申请日：2012-05-03

Applicant: Badih EL-KAREH ,  JONG HO LEE ,  DONGSEOK KIM ,  CHANG EUN LEE ,  Jung-Joo KIM

Inventor： Badih EL-KAREH ,  JONG HO LEE ,  DONGSEOK KIM ,  CHANG EUN LEE ,  Jung-Joo KIM

IPC: H01L29/86 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L28/60

Abstract: A high-precision capacitor includes a first degenerately doped polysilicon plate, a second degenerately doped polysilicon plate, and a dielectric material disposed between the first and the second degenerately doped polysilicon plates. The first degenerately doped polysilicon plate may be formed by performing POCL (phosphorus oxychloride) diffusion, and performing ion implantation through the POCL oxide to replenish the loss of dopants. The second degenerately doped polysilicon plate may be formed by performing POCL doping. The high-precision capacitor may exhibit a voltage coefficient of capacitance (VCC) comparable to a Metal-Insulator-Metal capacitor, however, with a dielectric of higher quality.

Abstract translation: 高精度电容器包括第一简并掺杂多晶硅板，第二简并掺杂多晶硅板和设置在第一和第二简并掺杂多晶硅板之间的电介质材料。 可以通过进行POCL（三氯氧化磷）扩散，并通过POCL氧化物进行离子注入以补充掺杂剂的损失来形成第一个简并掺杂的多晶硅板。 可以通过执行POCL掺杂来形成第二简并掺杂多晶硅板。 高精度电容器可以表现出与金属 - 绝缘体 - 金属电容器相当的电容（VCC）电压系数，然而，具有更高质量的电介质。