公开(公告)号：US20230292528A1

公开(公告)日：2023-09-14

申请号：US17654777

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jordan KATINE ,  Lei WAN

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L27/224 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/161

Abstract: Selector material layers are formed over the first electrically conductive lines, and magnetic tunnel junction material layers are formed over the selector material layers. The magnetic tunnel junction material layers are patterned into a two-dimensional array of magnetic tunnel junction (MTJ) pillar structures. A dielectric spacer material layer is deposited over the two-dimensional array of MTJ pillar structures. The dielectric spacer material layer and the selector material layers are anisotropically etched. Patterned portions of the selector material layers include a two-dimensional array of selector-containing pillar structures. Second electrically conductive lines are formed over the two-dimensional array of MTJ pillar structures.

公开(公告)号：US20230284443A1

公开(公告)日：2023-09-07

申请号：US17684975

申请日：2022-03-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo OKINA ,  Shinsuke YADA ,  Ryo YOSHIMOTO

IPC: H01L27/11556 ,  G11C16/04 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/80001 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1451

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.

公开(公告)号：US11749600B2

公开(公告)日：2023-09-05

申请号：US17224370

申请日：2021-04-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.

公开(公告)号：US20230268015A1

公开(公告)日：2023-08-24

申请号：US17678584

申请日：2022-02-23

Applicant: SanDisk Technologies LLC.

Inventor： Ke Zhang ,  Minna Li ,  Liang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.

公开(公告)号：US20230260589A1

公开(公告)日：2023-08-17

申请号：US17672904

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

公开(公告)号：US20230259149A1

公开(公告)日：2023-08-17

申请号：US17672961

申请日：2022-02-16

Applicant: SanDisk Technologies LLC

Inventor： James O'Toole ,  Ward Parkinson ,  Thomas Trent

IPC: G05F3/26

CPC classification number: G05F3/26

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

公开(公告)号：US20230253056A1

公开(公告)日：2023-08-10

申请号：US17665267

申请日：2022-02-04

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/14 ,  G11C16/28 ,  G11C16/102 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.

公开(公告)号：US20230253048A1

公开(公告)日：2023-08-10

申请号：US17667100

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Ravi Kumar

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/32 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11556

Abstract: The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.

公开(公告)号：US11721727B2

公开(公告)日：2023-08-08

申请号：US17001117

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/417 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/41741 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

公开(公告)号：US20230223356A1

公开(公告)日：2023-07-13

申请号：US17574182

申请日：2022-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shin SAKIYAMA ,  Genta MIZUNO ,  Kenzo IIZUKA ,  Takayuki YOKOYAMA ,  Toshiyuki SEGA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2924/14511

Abstract: A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal direction by line trenches that laterally extend along the first horizontal direction. Arrays of memory stack structures are provided such that each array of memory stack structures among the arrays of memory stack structures vertically extends through a respective alternating stack. Each of the memory stack structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.