公开(公告)号：US09780208B1

公开(公告)日：2017-10-03

申请号：US15212755

申请日：2016-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US09735242B2

公开(公告)日：2017-08-15

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

公开(公告)号：US09722053B1

公开(公告)日：2017-08-01

申请号：US15075557

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US20170207122A1

公开(公告)日：2017-07-20

申请号：US15470006

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.

公开(公告)号：US20170141211A1

公开(公告)日：2017-05-18

申请号：US15168690

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

公开(公告)号：US20170117156A1

公开(公告)日：2017-04-27

申请号：US14920179

申请日：2015-10-22

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Catherine B. Labelle

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/31053 ,  H01L21/31127 ,  H01L21/31144 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET devices and methods of fabricating a FinFET device are provided. An exemplary method of fabricating a FinFET device includes providing a semiconductor substrate with a plurality of fins and a multi-layered hardmask stack formed thereover. The multi-layered hardmask stack is patterned to form a patterned multi-layered hardmask stack having a tapered fin masking configuration with a shortened region and an elongated region. A region of fins adjacent to the shortened region is masked with a second mask. The region of fins masked with the second mask is free from the patterned multi-layered hardmask stack. Fins in unmasked areas are etched after forming the second mask. The second mask is removed with at least one layer of the patterned multi-layered hardmask stack remaining after etching the fins in the unmasked areas. End portions of the fins adjacent to the shortened region are etched after removing the second mask.

公开(公告)号：US09613962B2

公开(公告)日：2017-04-04

申请号：US15172201

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Neeraj Tripathi

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/165 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/66818

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

公开(公告)号：US09502286B2

公开(公告)日：2016-11-22

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09478538B1

公开(公告)日：2016-10-25

申请号：US14820661

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L27/088 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。

公开(公告)号：US20160254192A1

公开(公告)日：2016-09-01

申请号：US14633544

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Catherine B. Labelle

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/76224 ,  H01L21/823481

Abstract: A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in the first subset exposed by a first opening in the first mask layer are removed to define, for each of the fins, a first fin segment and a second fin segment, each having a cut end surface. A first liner layer is formed on at least the cut end surface of the first fin segment for each of the fins in the first subset. A second mask layer having a second opening is formed above a second subset of the plurality of fins. An etching process removes second portions of the second subset of fins exposed by the second opening. The first liner layer protects the cut end surface of at least the first fin segment during the removing.

Abstract translation: 一种方法包括在衬底上形成多个翅片。 第一掩模层形成在翅片的第一子集上方。 移除在第一掩模层中由第一开口暴露的第一子集中的翅片的第一部分，以为每个翅片限定每个具有切割端面的第一翅片段和第二翅片段。 在第一子集中的每个鳍​​片的至少第一鳍片段的切割端表面上形成第一衬里层。 具有第二开口的第二掩模层形成在多个翅片的第二子集之上。 蚀刻工艺除去由第二开口暴露的第二翅片子集的第二部分。 在移除期间，第一衬里层保护至少第一鳍段的切割端表面。