公开(公告)号：US20180254291A1

公开(公告)日：2018-09-06

申请号：US15966231

申请日：2018-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US20180005668A1

公开(公告)日：2018-01-04

申请号：US15626595

申请日：2017-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Takanori MATSUZAKI

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C11/403 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  H01L21/8258 ,  H01L27/0222 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24 ,  H01L29/7869

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

公开(公告)号：US20170301380A1

公开(公告)日：2017-10-19

申请号：US15635550

申请日：2017-06-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: G11C7/10 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  G11C8/08 ,  G11C7/22 ,  G11C7/18 ,  H01L29/786 ,  G11C7/12

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

公开(公告)号：US20170271516A1

公开(公告)日：2017-09-21

申请号：US15451514

申请日：2017-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L29/786 ,  G11C16/04 ,  H01L27/11563 ,  H01L29/24 ,  H01L27/11517

CPC classification number: H01L29/7869 ,  G11C11/401 ,  G11C11/404 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0466 ,  G11C2213/79 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24

Abstract: A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

公开(公告)号：US20170230041A1

公开(公告)日：2017-08-10

申请号：US15427815

申请日：2017-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L21/78 ,  H01L23/498

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US20170186749A1

公开(公告)日：2017-06-29

申请号：US15383274

申请日：2016-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L27/105 ,  H01L27/11 ,  H01L27/108 ,  G06F1/32 ,  H01L23/528 ,  G11C5/06 ,  G11C5/14 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C5/06 ,  G11C5/14 ,  G11C7/04 ,  G11C11/401 ,  G11C11/4074 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/1225 ,  H01L29/7851 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

公开(公告)号：US20170179294A1

公开(公告)日：2017-06-22

申请号：US15380502

申请日：2016-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI ,  Haruyuki BABA ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/088

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

公开(公告)号：US20170162603A1

公开(公告)日：2017-06-08

申请号：US15366418

申请日：2016-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Masayuki SAKAKURA

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US20170117283A1

公开(公告)日：2017-04-27

申请号：US15296493

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Kiyoshi KATO

IPC: H01L27/115 ,  H01L29/792 ,  H01L23/535 ,  H01L27/12

CPC classification number: G11C16/0433 ,  G11C11/403 ,  G11C11/4097 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/792

Abstract: The memory device includes a first transistor and a circuit. The circuit includes a second to a (2n+1)th transistor, a first to an n-th capacitor, a first wiring, and a first to an n-th retention node (n is an integer greater than or equal to 2). When n is 2, a memory cell MC[1] includes a transistor ROS[1], a transistor WOS[1], and a capacitor C[1] and a memory cell MC[2] includes a transistor ROS[2], a transistor WOS [2], and a capacitor C[2]. A back gate of the transistor WOS[1] and a back gate of the transistor WOS[2] are electrically connected to a wiring WBG. A bake gate of a first transistor, a back gate of the transistor ROS[1], and a back gate of the transistor ROS[2] are electrically connected to a wiring RBG.

公开(公告)号：US20170062044A1

公开(公告)日：2017-03-02

申请号：US15260400

申请日：2016-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: G11C11/419 ,  H01L21/02 ,  H01L29/786 ,  H01L27/11 ,  G11C11/418 ,  H01L27/12

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。