公开(公告)号：US5415555A

公开(公告)日：1995-05-16

申请号：US200037

申请日：1994-02-22

Applicant: Mohi Sobhani

Inventor： Mohi Sobhani

IPC: H01R12/71 ,  H01R43/00 ,  H05K1/14 ,  H05K3/00 ,  H05K3/36 ,  H05K3/40 ,  H01R9/09

CPC classification number: H05K3/4007 ,  H01R12/714 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/09745 ,  H05K2203/167 ,  H05K3/0094 ,  Y10T29/49155

Abstract: A pair of electrical circuits (20, 22), which may be both flexible or one flexible and one rigid, are interconnected by projections, such as bumps (24) and rings (26) . The projections are formed from substantially inelastic dielectric material, such as an epoxy defining bumps (34) and rings (36), which are plated with copper (38). Projections (24, 26) of one circuit are disposed to interconnect with mating projections on the other circuit, the interconnection being bump to bump, bump to ring, or bump to pad. The projections may be formed on a copper-clad substrate (42) or on plated-through holes (72) on a printed wiring board (70). Alternately, polygonal pads (94) on a circuit (90) may be joined to a projection. Further, a plurality of bump projections (106), electrically connected to the same or different circuits, may collectively interconnect with a single oval ring projection (108).

Abstract translation: 可以是柔性的或一个柔性的，一个刚性的一对电路（20,22）通过诸如凸块（24）和环（26）的突起互连。 突起由基本上非弹性的电介质材料形成，例如镀有铜（38）的环氧树脂定义凸块（34）和环（36）。 一个电路的投影（24,26）被布置成与另一个电路上的配合突起相互连接，互连件碰撞，碰撞到环或撞击到焊盘。 突起可以形成在覆铜基板（42）上或印刷电路板（70）上的电镀通孔（72）上。 或者，电路（90）上的多边形焊盘（94）可以连接到突起。 此外，电连接到相同或不同电路的多个凸起突起（106）可以与单个椭圆形环形突起（108）共同互连。

公开(公告)号：US5375039A

公开(公告)日：1994-12-20

申请号：US127150

申请日：1993-09-27

Applicant: Thomas Wiesa

Inventor： Thomas Wiesa

IPC: H05K1/02 ,  H05K3/42 ,  H05K7/20 ,  H05H7/20

CPC classification number: H05K1/0206 ,  H05K7/205 ,  H05K1/0272 ,  H05K2201/0338 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K3/0061 ,  H05K3/42

Abstract: A circuit board layering arrangement is capable of dissipating, into a heat sink, the heat produced by power components mounted on the circuit board, without permitting the short circuiting of electricity between the power components and other components or the heat sink. The arrangement comprises a circuit board, at least one power component and a heat sink. A plurality of through contacts are introduced into the circuit board, and a plurality of conductive tracks are disposed on first and second surfaces of the circuit board. The plurality of conductive tracks include two large-surface conductive tracks, one on each surface of the circuit board. One or more power components are surface-mounted on a first surface of the circuit board on a first large-surface conductive track. The second large-surface conductive track is thermally coupled to the first large-surface conductive track and to the heat sink. A layer of metal, preferably copper, may be disposed between the second large-surface conductive track and the heat sink, and a layer of glass cloth may be disposed between the second large-surface conductive track and the layer of metal.

Abstract translation: 电路板层叠装置能够将安装在电路板上的功率部件产生的热量散发到散热器中，而不会使功率部件和其它部件或散热器之间的电短路。 该装置包括电路板，至少一个功率部件和散热器。 多个贯通接点被引入到电路板中，并且多个导电轨道设置在电路板的第一和第二表面上。 多个导电轨道包括两个大表面导电轨道，一个在电路板的每个表面上。 一个或多个功率部件被表面安装在第一大表面导电轨道上的电路板的第一表面上。 第二大表面导电轨道热耦合到第一大表面导电轨道和散热器。 可以在第二大表面导电轨道和散热器之间设置金属层，优选铜层，并且可以在第二大表面导电轨道和金属层之间设置一层玻璃布。

公开(公告)号：US5196990A

公开(公告)日：1993-03-23

申请号：US857125

申请日：1992-03-25

Applicant: Toshio Kurosaki

Inventor： Toshio Kurosaki

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0216 ,  H05K1/0203 ,  H05K1/0272 ,  H05K2201/09745 ,  H05K3/0061

Abstract: A metal printed board having circuit conductors on the surface of an insulating plate layered on a metal plate, wherein grooves formed in the portions of the metal plate which face the circuit conductor. The electronic parts mounted conducts into the metal plate through the solder portions and the insulating plate just thereunder. Accordingly, the presence of the grooves little impairs the thermal conduction. The stray capacitance between the conductor circuit and the metal plate because of the formed grooves, is considerably reduced, so that the signal leakage and noise sneaking are minimized.

Abstract translation: 一种金属印刷电路板，其在位于金属板上的绝缘板的表面上具有电路导体，其中形成在金属板的与电路导体相对的部分中的沟槽。 安装的电子部件通过焊接部分和绝缘板正下方进入金属板。 因此，凹槽的存在几乎不会损害热传导。 导体电路和金属板之间的杂散电容由于形成的沟槽而大大减小，从而使信号泄漏和噪声潜流最小化。

公开(公告)号：US3982271A

公开(公告)日：1976-09-21

申请号：US548010

申请日：1975-02-07

Applicant: Daniel Olivieri ,  Robert James Socci

Inventor： Daniel Olivieri ,  Robert James Socci

IPC: H01L23/32 ,  H01L23/36 ,  H01L23/373 ,  H01L23/40 ,  H01L23/66 ,  H05K1/02 ,  H05K1/18 ,  H01L23/02 ,  H01P3/08

CPC classification number: H05K1/021 ,  H01L23/32 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/66 ,  H01L2023/405 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/182 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2201/10409 ,  H05K3/0061

Abstract: An apparatus for heat spreading and low parasitic transistor mounting in high power microstrip circuit applications. An electrically and thermally conductive strip is conductively affixed to the ground plane of a substrate containing the circuit. The strip is shaped to fit substantially within a slot in a circuit carrier block (heat sink) such that the strip makes intimate contact between the mounting surface of the transistor mounted in the slot and the carrier block. The strip provides the electrical connection between the ground plane of the substrate and the carrier block in addition to increasing the surface area for more efficient heat transfer, and thus, allows for the ground plane of the substrate to be attached to the block either by a non-metallic adhesive or by solder.

Abstract translation: 一种在大功率微带电路应用中散热和低寄生晶体管安装的装置。 电导热导电带导电地固定到包含电路的基板的接地平面上。 条带被成形为基本上配合在电路载体块（散热器）中的狭槽内，使得条带在安装在槽中的晶体管的安装表面与载体块之间进行紧密接触。 除了增加表面积以更有效地传热之外，带还提供了衬底的接地平面和载体块之间的电连接，因此允许衬底的接地平面通过一个 非金属粘合剂或焊料。

公开(公告)号：US3813773A

公开(公告)日：1974-06-04

申请号：US28616372

申请日：1972-09-05

Applicant: BUNKER RAMO

Inventor： PARKS H

IPC: H05K3/36 ,  H01L23/04 ,  H05K1/16 ,  H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/44 ,  H05K3/46 ,  H01R9/00

CPC classification number: H05K3/445 ,  H05K3/041 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4614 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/0369 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A low-cost method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure comprised of a plurality of electrically conductive wafers stacked together under pressure. A stack is normally comprised of conductive wafers of different types including component wafers, interconnection wafers, and connector wafers which are fabricated to provide X, Y and Z-axis coaxial connections between components in the stack. In accordance with the present invention, these X, Y and Z coaxial connections are fabricated directly from the wafer material itself at relatively low cost as compared to known methods as a result of the employment of a novel combination of precision stamping, dielectric filling and sanding or etching steps.

Abstract translation: 一种采用精密冲压的低成本方法，用于制造由在压力下堆叠在一起的多个导电晶片组成的多晶圆电路结构的晶片。 堆叠通常由不同类型的导电晶片组成，包括组件晶片，互连晶片和连接器晶片，其被制造为在堆叠中的组件之间提供X，Y和Z轴同轴连接。 根据本发明，与已知方法相比，这些X，Y和Z同轴连接直接从晶片材料本身以相对较低的成本制造，因为采用精密冲压，电介质填充和打磨的新颖组合 或蚀刻步骤。

公开(公告)号：US3778530A

公开(公告)日：1973-12-11

申请号：US3778530D

申请日：1972-07-05

Applicant: REIMANN W

Inventor： REIMANN W

IPC: H05K1/11 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K7/10

CPC classification number: H05K3/3421 ,  H05K1/111 ,  H05K3/062 ,  H05K3/064 ,  H05K3/108 ,  H05K3/243 ,  H05K7/1023 ,  H05K2201/0305 ,  H05K2201/0338 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/048 ,  H05K2203/058 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed circuit board for mounting integrated circuit and resistor network packages commonly referred to as flatpack components and a process for fabricating the circuit board. The printed circuit board has a conductive pattern of electrical connection pads for connecting to electrical leads from flatpack components and electrical conductors for connecting the pads to circuitry external to the board. A channel for receiving and aligning each electrical lead from a flatpack component is formed by printed circuit techniques. The surface layer of each channel is formed of solder which simplifies the process of electrically connecting flatpack leads and reduces errors occuring in the soldering process.

Abstract translation: 用于安装通常称为扁平封装部件的集成电路和电阻器网络封装的印刷电路板以及用于制造电路板的工艺。 印刷电路板具有电连接焊盘的导电图案，用于连接到来自扁平封装部件和电导体的电引线，用于将焊盘连接到板外部的电路。 用于通过印刷电路技术形成用于从扁平封装部件接收和对准每个电引线的通道。 每个通道的表面层由焊料形成，这简化了电连接扁平封装引线的过程，并减少了焊接过程中发生的错误。

公开(公告)号：US3351953A

公开(公告)日：1967-11-07

申请号：US53337566

申请日：1966-03-10

Applicant: BUNKER RAMO

Inventor： SEAR BRIAN E

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K1/0221 ,  H01R12/523 ,  H05K1/09 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/09745 ,  H05K2203/0323 ,  H05K2203/0369 ,  H05K2203/061 ,  H05K2203/143

公开(公告)号：US3324224A

公开(公告)日：1967-06-06

申请号：US48426565

申请日：1965-09-01

Applicant: RAYTHEON CO

Inventor： THIBODEAN WILLIAM L

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/44 ,  H05K9/00

CPC classification number: H05K1/0221 ,  H05K3/107 ,  H05K3/445 ,  H05K9/0039 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/09745 ,  H05K2201/09809 ,  H05K2201/1028

公开(公告)号：US20190157541A1

公开(公告)日：2019-05-23

申请号：US16257252

申请日：2019-01-25

Applicant: BROTHER KOGYO KABUSHIKI KAISHA

Inventor： Toru KAKIUCHI

IPC: H01L41/047 ,  B41J2/14 ,  B41J2/16 ,  B41J2/175 ,  H05K3/36 ,  H05K3/32

CPC classification number: H01L41/0475 ,  B41J2/14072 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1643 ,  B41J2/17526 ,  B41J2/1753 ,  B41J2002/14491 ,  H01L41/0973 ,  H05K3/321 ,  H05K3/361 ,  H05K2201/0233 ,  H05K2201/09745 ,  H05K2203/0278

Abstract: An actuator device includes: an actuator including a first contact; and a wire member including a second contact connected to the first contact with a conductive adhesive including a conductive particle. One of the first contact and the second contact is a particular contact. The other of the first contact and the second contact is a specific contact. At least two protrusions and at least one recess are formed on and in the particular contact. The at least two protrusions are arranged in a first direction. The at least one recess is interposed between the at least two protrusions. The particular contact is joined to the specific contact with the conductive adhesive provided in the at least one recess, in a state in which each of the at least two protrusions is in contact with the specific contact.

公开(公告)号：US20180359849A1

公开(公告)日：2018-12-13

申请号：US15805195

申请日：2017-11-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akira TANAKA ,  Masaya HIRASHIMA ,  Satoru YASUI ,  Shukuyo YAMADA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/0271 ,  H05K1/111 ,  H05K1/183 ,  H05K3/34 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09745 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/2009 ,  H05K2203/0195 ,  H05K2203/0278

Abstract: According to one embodiment, provided are an electronic device and an electronic component protection substrate in which an electronic component is prevented from entering an irregular state. According to the electronic device of the present embodiment, an electronic component is soldered onto a pattern line of a printed circuit substrate, and a surface of the printed circuit substrate where the electronic component is disposed is formed as a recess such that the thickness of the printed circuit substrate in the recess part is thinned.