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    Memory operation latency control
    151.
    发明授权
    Memory operation latency control 有权
    内存操作延迟控制

    公开(公告)号：US09437264B2

    公开(公告)日：2016-09-06

    申请号：US15055329

    申请日：2016-02-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Han-Sung Chen ,  Ming-Chao Lin

    IPC: G11C8/08 ,  G11C16/30 ,  G11C7/22

    CPC classification number: G11C7/22 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2272 ,  G11C2207/2281

    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

    Abstract translation: 具有存储器的集成电路可以在诸如读取操作的连续操作之间以较低的延迟进行操作。 第一次，在集成电路上的存储器阵列上完成第一操作命令。 第二次，在存储器阵列上开始第二操作命令。 来自电荷泵的稳定的输出电压被耦合到存储器阵列中的字线。 从第一次到第二次，稳定的输出电压保持在诸如读取电压的字线操作电压。

    THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE
    152.
    发明申请
    THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE 有权
    存储器电池的阈值电压分组在相同的阈值电压范围内

    公开(公告)号：US20160125922A1

    公开(公告)日：2016-05-05

    申请号：US14533936

    申请日：2014-11-05

    Applicant: Macronix International Co., Ltd.

    Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC: G11C7/10 ,  G11C7/08 ,  G11C7/12

    CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3481 ,  G11C2211/5642

    Abstract: A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.

    Abstract translation: 正在进行编程的存储单元被确定为属于划分特定存储单元的当前阈值电压范围的多个第二阈值电压范围中的特定的一个。 施加编程脉冲以将特定存储器单元编程到目标阈值电压范围内。 根据存储单元的特定的第二阈值电压范围，施加到特定存储单元的编程脉冲的编程电压和总持续时间中的至少一个是不同的。

    Staggered write and verify for phase change memory
    154.
    发明授权
    Staggered write and verify for phase change memory 有权
    交错写入和验证相变存储器

    公开(公告)号：US09159412B1

    公开(公告)日：2015-10-13

    申请号：US14331487

    申请日：2014-07-15

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Tien-Yen Wang

    IPC: G11C11/34 ,  G11C13/00

    CPC classification number: G11C13/0064 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0092

    Abstract: A method for storing a data value in a memory cell is provided. The data value includes one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges. The method includes, within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period. The write cycle is shorter than a sum of the first write period and the second verify period.

    Abstract translation: 提供了一种用于将数据值存储在存储单元中的方法。 数据值包括分别由第一和第二可编程电阻范围表示的第一数据值和第二数据值之一。 该方法包括在写入周期内，通过应用具有第一验证周期的第一验证操作和具有第一写入周期的第一写入操作或将第二数据值存储在存储器单元中来将第一数据值存储在存储器单元中 通过应用具有比第一验证周期长的第二验证周期的第二验证操作和具有比第一写入周期短的第二写入周期的第二写入操作。 写周期比第一写入周期和第二验证周期的和短。

    Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
    156.
    发明授权
    Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits 有权
    用于调整具有寻址和相邻位的存储单元的漏极偏置的方法和装置

    公开(公告)号：US09117492B2

    公开(公告)日：2015-08-25

    申请号：US14556973

    申请日：2014-12-01

    Applicant: Macronix International Co., Ltd.

    Inventor： Han-Sung Chen ,  Chung-Kuang Chen ,  Chun-Hsiung Hung

    IPC: G11C7/00 ,  G11C7/22 ,  G11C11/56

    CPC classification number: G11C7/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C2211/5621

    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.

    Abstract translation: 诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。 在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。 如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。 该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。

    Serial peripheral interface and method for data transmission
    158.
    发明授权
    Serial peripheral interface and method for data transmission 有权
    串行外设接口和数据传输方法

    公开(公告)号：US09075925B2

    公开(公告)日：2015-07-07

    申请号：US13687586

    申请日：2012-11-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Lan Kuo ,  Chun-Hsiung Hung

    IPC: G06F13/14 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

    CPC classification number: G06F13/4291 ,  G06F1/22 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/404

    Abstract: A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.

    Abstract translation: 提供了包括多个引脚和时钟引脚的集成电路的串行外设接口。 引脚耦合到集成电路，用于发送指令，地址或读出数据。 时钟引脚耦合到集成电路，用于输入多个定时脉冲。 多个引脚在定时脉冲的上升沿，下降沿或两个边缘发送指令，地址或读出数据。

    MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING
    159.
    发明申请
    MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING 审中-公开
    三维阵列与存储器中的二极管的存储器架构

    公开(公告)号：US20150123192A1

    公开(公告)日：2015-05-07

    申请号：US14590273

    申请日：2015-01-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

    IPC: H01L27/115 ,  H01L21/768

    CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

    Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

    PLURAL OPERATION OF MEMORY DEVICE
    160.
    发明申请
    PLURAL OPERATION OF MEMORY DEVICE 审中-公开
    存储设备的多重操作

    公开(公告)号：US20150063023A1

    公开(公告)日：2015-03-05

    申请号：US14535042

    申请日：2014-11-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Tzung Shen Chen ,  Shuo Nan Hong ,  Yi Ching Liu ,  Chun-Hsiung Hung

    IPC: G11C16/26 ,  G11C16/10

    CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3422 ,  G11C16/3427 ,  G11C16/3431

    Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.

    Abstract translation: 集成电路器件包括半导体衬底，衬底上的第一存储器块，包括NAND存储器单元，在衬底上的第二存储器块，包括NAND存储器单元，以及控制器电路。 第一和第二存储器块可配置为响应于第一操作算法存储用于第一数据使用模式的数据以读取，编程和擦除数据，以及响应于第二操作算法读取数据使用的第二模式 ，分别编程和擦除数据。 控制器电路耦合到第一和第二存储器块，并且被配置为执行第一和第二操作算法，其中在第一操作算法中应用的读操作的字线通过电压处于比第二字的较低电压电平 用于在第二操作算法中应用的读操作的线通电压。

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