公开(公告)号：US12022659B2

公开(公告)日：2024-06-25

申请号：US17874844

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C11/2255 ,  H01L23/5226 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/78391 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240194234A1

公开(公告)日：2024-06-13

申请号：US18443997

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US11935624B2

公开(公告)日：2024-03-19

申请号：US18302560

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  H01L21/822

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

公开(公告)号：US20240015976A1

公开(公告)日：2024-01-11

申请号：US18152585

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chia-En Huang ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/5283

Abstract: In an embodiment, a device includes a first gate structure over a substrate, the first gate structure including a first gate electrode over a first side of a first gate dielectric; a first electrode and a second electrode disposed over a second side of the first gate dielectric opposite the first side; a second gate structure disposed between the first electrode and the second electrode, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric at least laterally surrounding the second gate electrode; and a semiconductor film disposed between the first electrode and the second electrode and at least laterally surrounding the second gate structure, wherein at least one of the first gate dielectric or the second gate dielectric is a memory film.

公开(公告)号：US11854823B2

公开(公告)日：2023-12-26

申请号：US17574414

申请日：2022-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chih-Pin Huang ,  Ching-Wen Chan

IPC: H01L21/3105 ,  H01L21/308 ,  H01L21/762 ,  H10B41/30

CPC classification number: H01L21/31056 ,  H01L21/3086 ,  H01L21/76283 ,  H10B41/30

Abstract: An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.

公开(公告)号：US20230369053A1

公开(公告)日：2023-11-16

申请号：US18359507

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/28185 ,  H01L21/823462 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42376

Abstract: Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

公开(公告)号：US20230309315A1

公开(公告)日：2023-09-28

申请号：US18327439

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L21/02 ,  H01L29/24 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/02565 ,  H01L29/24 ,  H01L23/5226 ,  H10B51/30

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

公开(公告)号：US11729997B2

公开(公告)日：2023-08-15

申请号：US17229395

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/24 ,  H10B63/00 ,  H01L29/24 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/861 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/06 ,  H10B43/20 ,  H10N70/00 ,  H10B43/35 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/02565 ,  H01L21/8221 ,  H01L21/823475 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/861 ,  H10B43/20 ,  H10B63/20 ,  H10B63/30 ,  H10N70/011 ,  H10B43/35 ,  H10N70/20

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

公开(公告)号：US11688784B2

公开(公告)日：2023-06-27

申请号：US17218307

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/665

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an isolation structure arranged within a substrate. The isolation structure has one or more surfaces defining one or more trenches that are recessed below an uppermost surface of the isolation structure and that are disposed along opposing sides of an active region of the substrate. A conductive gate is arranged over the substrate between a source region and a drain region. The conductive gate extends into the one or more trenches disposed along opposing sides of the active region of the substrate. The conductive gate has an upper surface that continuously extends past opposing sides of the one or more trenches.

公开(公告)号：US11657863B2

公开(公告)日：2023-05-23

申请号：US17397414

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: G11C8/08 ,  G11C29/50 ,  G11C29/02 ,  H01L21/822 ,  G11C29/12

CPC classification number: G11C8/08 ,  G11C29/025 ,  G11C29/12 ,  G11C29/50 ,  H01L21/8221 ,  G11C2029/1202

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.