公开(公告)号：US20190123016A1

公开(公告)日：2019-04-25

申请号：US16221986

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/2076 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.

公开(公告)号：US20170005060A1

公开(公告)日：2017-01-05

申请号：US15268693

申请日：2016-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Bor-Rung Su

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/482

CPC classification number: H01L24/16 ,  H01L21/28 ,  H01L21/302 ,  H01L21/565 ,  H01L21/76895 ,  H01L23/48 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/538 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.

Abstract translation: 本公开涉及集成芯片封装装置。 在一些实施例中，包装装置具有第一包装部件。 金属痕迹布置在第一包装部件的表面上。 金属痕迹有底切。 成型材料填充金属迹线的底切，并且具有倾斜的最外侧壁，其高度从金属迹线的顶表面下方的位置单调地降低到第一包装部件的表面。 焊料区域布置在金属迹线上方。