公开(公告)号：US20240021576A1

公开(公告)日：2024-01-18

申请号：US18365999

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chuan-An Cheng ,  Sung-Feng Yeh ,  Chih-Chia Hu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/565 ,  H01L21/568 ,  H01L24/80 ,  H01L25/50 ,  H01L24/08 ,  H01L2221/68372 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

公开(公告)号：US11854990B2

公开(公告)日：2023-12-26

申请号：US17176299

申请日：2021-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/07 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2224/73203 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20230395573A1

公开(公告)日：2023-12-07

申请号：US18366747

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/544 ,  H01L21/768 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L23/481 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L21/76898 ,  H01L21/6835 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/80 ,  H01L25/50 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2223/54426

Abstract: A semiconductor package includes a first die, a second die, an encapsulating material, and a redistribution structure. The second die is disposed over the first die and includes a plurality of bonding pads bonded to the first die, a plurality of through vias extending through a substrate of the second die and a plurality of alignment marks, wherein a pitch between adjacent two of the plurality of alignment marks is different from a pitch between adjacent two of the plurality of through vias. The encapsulating material is disposed over the first die and at least laterally encapsulating the second die. The redistribution structure is disposed over the second die and the encapsulating material and electrically connected to the plurality of through vias.

公开(公告)号：US11823989B2

公开(公告)日：2023-11-21

申请号：US17135435

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L21/762

CPC classification number: H01L23/49827 ,  H01L21/7684 ,  H01L21/76224 ,  H01L21/76846

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US11810899B2

公开(公告)日：2023-11-07

申请号：US17140547

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/568 ,  H01L21/7684 ,  H01L21/76885 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/09 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/02373 ,  H01L2224/03002 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/18 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/82 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/2011 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109

Abstract: A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

公开(公告)号：US11810883B2

公开(公告)日：2023-11-07

申请号：US17325649

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/24 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/25 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/2402 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die structure and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die structure.

公开(公告)号：US20230352439A1

公开(公告)日：2023-11-02

申请号：US18338107

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L24/80 ,  H01L25/0657 ,  H01L24/08 ,  H01L25/50 ,  H01L21/78 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US11756907B2

公开(公告)日：2023-09-12

申请号：US17673953

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L24/05 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5384

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

公开(公告)号：US11756901B2

公开(公告)日：2023-09-12

申请号：US17881739

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Chun-Chiang Kuo ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/585 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/09 ,  H01L24/33 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0649 ,  H01L23/562 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2224/94 ,  H01L2224/80

Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

公开(公告)号：US20230139919A1

公开(公告)日：2023-05-04

申请号：US17580942

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: Seamless bonding layers in semiconductor packages and methods of forming the same are disclosed. In an embodiment, a method includes forming a second passivation layer over a first metal pad and a second metal pad, the first metal pad and the second metal pad being disposed over a first passivation layer of a first semiconductor die; depositing a first bonding material over the second passivation layer to form a first portion of a first bonding layer, wherein at least a portion of a seam in the first bonding layer is between the first metal pad and the second metal pad; thinning the first portion of the first bonding layer to create a first opening from the seam; and re-depositing the first bonding material to fill the first opening and to form a second portion of the first bonding layer.