公开(公告)号：US20060157534A1

公开(公告)日：2006-07-20

申请号：US11195438

申请日：2005-08-02

Applicant: Masud Beroz

Inventor： Masud Beroz

IPC: B23K1/08 ,  B23K37/06

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K2101/40 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09245 ,  H05K2201/09427 ,  H05K2201/099 ,  Y02P70/613

Abstract: In a surface mounting operation for connecting a semiconductor chip and connection component, at least one of the chip or the component has a plurality of elongated pads having a length being greater than the width. The elongated pads are preferably parallel to each other on the chip or component. A solder mask layer may be placed over a selected number of the pads before a bonding operation. The solder mask layer preferably has elongated apertures which are arranged in a perpendicular fashion to the elongated pads. A slight misalignment of the solder mask will not affect the surface area of the pad that shows through the elongated apertures of the solder mask.

Abstract translation: 在用于连接半导体芯片和连接部件的表面安装操作中，芯片或部件中的至少一个具有长度大于宽度的多个细长焊盘。 细长垫优选在芯片或部件上彼此平行。 焊接掩模层可以在接合操作之前放置在选定数量的焊盘上。 焊接掩模层优选地具有细长的孔，其以垂直于细长垫的方式布置。 焊接掩模的轻微的未对准不会影响通过焊接掩模的细长孔显示的焊盘的表面积。

公开(公告)号：US20060121790A1

公开(公告)日：2006-06-08

申请号：US11208980

申请日：2005-08-22

Applicant: Amid Hashim

Inventor： Amid Hashim

IPC: H01R24/00

CPC classification number: H05K1/0228 ,  H01R4/242 ,  H01R13/6469 ,  H01R13/6658 ,  H01R24/64 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communications connector includes: a dielectric mounting substrate; at least four pairs of conductors mounted on the mounting substrate, each of the conductors including a free end segment, each of the free end segments being positioned in side-by-side and generally parallel relationship; and at least four pairs of terminals mounted on the mounting substrate, wherein each of the pairs of terminals is electrically connected to a respective pair of conductors. A first pair of conductor free end segments is immediately adjacent each other, a second pair of conductor free end segments is immediately adjacent each other and positioned one side of the first pair, a fourth pair of conductor free end segments is immediately adjacent each other and positioned on an opposite side of the first pair, and a third pair of conductor free end segments sandwiches the first pair, with one of the conductor free end segments of the third pair being disposed between the first and second pairs, and the other of the conductor free end segments being disposed between the first and fourth pairs. Each of the first, second and fourth pairs of conductors includes a crossover between the conductors of the pairs, and wherein the third pair of conductors includes two crossovers between its conductors.

Abstract translation: 通信连接器包括：电介质安装基板; 安装在所述安装基板上的至少四对导体，每个所述导体包括自由端段，每个所述自由端段以并排方式并且大致平行的关系定位; 以及安装在安装基板上的至少四对端子，其中每对端子电连接到相应的一对导体。 第一对导体自由端段彼此紧邻，第二对导体自由端段彼此紧邻并且位于第一对的一侧，第四对导体自由端段彼此紧邻， 定位在第一对的相对侧上，第三对导体自由端段夹住第一对，第三对中的一个导体自由端段设置在第一对和第二对之间，另一个 导体自由端段设置在第一和第四对之间。 第一，第二和第四对导体中的每一个包括在对的导体之间的交叉，并且其中第三对导体在其导体之间包括两个交叉。

公开(公告)号：US07026884B2

公开(公告)日：2006-04-11

申请号：US10329751

申请日：2002-12-27

Applicant: Ryszard Vogel

Inventor： Ryszard Vogel

IPC: H01P5/10

CPC classification number: H05K1/0228 ,  H01P5/187 ,  H05K1/0237 ,  H05K1/162 ,  H05K2201/09245

Abstract: The invention relates to a high frequency component of layered structure, and a method for manufacturing the component. The component comprises at least one dielectric layer parallel to the layers of the layered structure, at least two transmission lines for transmitting electrical signals, at least one capacitor, each of which is formed by overlapping parts of two transmission lines, the overlapping parts being for forming capacitive interaction between the parts, and the overlapping parts being arranged to overlap each other in a transversal direction to a dielectric layer parallel to the layers of the layered structure, the dielectric layer being in between the overlapping parts.

Abstract translation: 本发明涉及分层结构的高频分量及其制造方法。 该组件包括平行于分层结构的层的至少一个电介质层，用于传输电信号的至少两个传输线，至少一个电容器，每个电容器由两条传输线的重叠部分形成，重叠部分用于 在所述部分之间形成电容性相互作用，并且所述重叠部分被布置为在与所述层状结构的层平行的电介质层的横向方向上彼此重叠，所述电介质层位于所述重叠部分之间。

公开(公告)号：US06958941B2

公开(公告)日：2005-10-25

申请号：US10460293

申请日：2003-06-11

Applicant: Takayuki Honda

Inventor： Takayuki Honda

IPC: G11B20/24 ,  H05K1/02 ,  G11C7/00

CPC classification number: H05K1/0216 ,  G11B20/24 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2203/1572

Abstract: In a circuit board including an analog circuit and a digital circuit, the S/N ratio reduction resulting from the interference of digital signals with analog signals is suppressed. The circuit board includes a digital signal processing section forming part of the digital circuit, digital signal external conductors connected to the digital signal processing section, and digital signal output control means for interrupting the transmission of the digital signals from the digital signal processing section to the digital signal external conductors. A decrease in the limitation for the wiring pattern and the device arrangement provides an increase in the degree of freedom for designing, thereby making it possible to miniaturize the circuit board and to reduce the manufacturing cost thereof.

Abstract translation: 在包括模拟电路和数字电路的电路板中，由数字信号与模拟信号的干扰产生的S / N比减小被抑制。 电路板包括形成数字电路的一部分的数字信号处理部分，连接到数字信号处理部分的数字信号外部导体和用于中断数字信号从数字信号处理部分传输到数字信号处理部分的数字信号输出控制装置 数字信号外部导线。 布线图案和装置布置的限制的减少提高了设计的自由度，从而使得可以使电路板小型化并降低其制造成本。

公开(公告)号：US20040219342A1

公开(公告)日：2004-11-04

申请号：US10750560

申请日：2003-12-31

Inventor： David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary Paek

IPC: B32B003/00

CPC classification number: H05K1/112 ,  H05K3/4076 ,  H05K3/421 ,  H05K2201/09245 ,  H05K2201/09472 ,  H05K2201/09509 ,  Y10T428/24917

Abstract: An electronic substrate for interconnecting electronic components comprises a substrate having one or more conductive inner layers and one or more interconnect cavities extending into the substrate to expose one or more of the inner layers.

Abstract translation: 用于互连电子部件的电子基板包括具有一个或多个导电内层的基板和延伸到基板中以暴露一个或多个内层的一个或多个互连腔。

公开(公告)号：US20040038598A1

公开(公告)日：2004-02-26

申请号：US10450527

申请日：2003-06-20

Inventor： Ernst Steiner ,  Dieter Stroh ,  Horst Dieterle

IPC: H01R009/22

CPC classification number: B29C65/082 ,  B23K20/10 ,  B23K20/106 ,  B23K2101/38 ,  B29C66/1122 ,  B29C66/43 ,  H01R4/021 ,  H01R12/59 ,  H01R43/0207 ,  H01R43/0228 ,  H01R43/0263 ,  H05K3/328 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2203/0195 ,  H05K2203/0285 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49194 ,  Y10T29/49208 ,  Y10T29/53217 ,  Y10T29/53243

Abstract: The invention relates to a method and device for connecting the electrical conductors which are surrounded by outer insulation and associated with overlapping flat conductors (47, 49) by means of a sonotrode (52) producing ultrasonic vibrations and a counter electrode associated therewith. The conductors which are to be connected are to be arranged on a surface (48) of a carrier (50) extending between the sonotrode and the counter electrode. The carrier can be embodied as a counter electrode.

Abstract translation: 本发明涉及一种用于连接电导体的方法和装置，所述电导体被外绝缘层包围，并通过产生超声波振动的超声波发生器（52）和与之相关联的反电极与重叠的扁平导体（47,49）相关联。 要连接的导体将被布置在延伸在超声焊丝和对电极之间的载体（50）的表面（48）上。 载体可以实现为对电极。

公开(公告)号：US20030231474A1

公开(公告)日：2003-12-18

申请号：US10173329

申请日：2002-06-14

Inventor： David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary I. Paek

IPC: H05K001/18

CPC classification number: H05K1/115 ,  H05K3/4644 ,  H05K2201/09245 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49126

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.

Abstract translation: 公开了一种电子组件。 电子组件包括下部和形成在下部的上表面上的第一细长迹线。 迹线被上部覆盖，并且通过上部的上表面形成的开口延伸到迹线以暴露迹线的一部分。 第二细长迹线形成在上部。 定位在通过上部的上表面形成的开口中的第二细长轨迹的一部分通过开口接触第一细长迹线，以在第一迹线和第二迹线之间形成电互连。

公开(公告)号：US20030213618A1

公开(公告)日：2003-11-20

申请号：US10145972

申请日：2002-05-14

Inventor： Claus Neesgaard

IPC: H05K007/06

CPC classification number: H05K1/0216 ,  H03F3/2173 ,  H05K2201/09245 ,  H05K2201/1003

Abstract: An audio amplifier output stage layout technique achieves minimum cross coupling between audio amplifier channels. Regarding TDAA output stages, the typical TDAA includes two demodulation inductors per audio channel. The two pair of demodulation inductors associated with the TDAA are arranged to form an X-pattern to simultaneously minimize cross coupling between audio amplifier channels and reduce PCB layout size.

Abstract translation: 音频放大器输出级布局技术实现音频放大器通道之间的最小交叉耦合。 关于TDAA输出级，典型的TDAA每个音频通道包括两个解调电感。 与TDAA相关联的两对解调电感器被布置成形成X图案，以同时最小化音频放大器通道之间的交叉耦合并且减小PCB布局尺寸。

公开(公告)号：US6132266A

公开(公告)日：2000-10-17

申请号：US477238

申请日：1995-06-07

Applicant: Daniel E. Klas ,  William J. Rose

Inventor： Daniel E. Klas ,  William J. Rose

IPC: H01R13/6469 ,  H01R13/6477 ,  H01R24/00 ,  H05K1/02 ,  H05K1/11 ,  H01R9/22

CPC classification number: H05K1/0228 ,  H01R13/6469 ,  H01R13/6477 ,  H05K1/117 ,  H05K2201/09245 ,  H05K2201/097 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A connector for communications systems has four input terminals and four output terminals, each arranged in an ordered array. A circuit electrically couples each input terminal to the respective output terminal and cancels crosstalk induced across the adjacent connector terminals. The circuit includes four conductive paths between the respective pairs of terminals. The first and third paths are in relatively close proximity and are substantially spaced from the second and fourth paths. The second and fourth paths are in relatively close proximity.

Abstract translation: 用于通信系统的连接器具有四个输入端子和四个输出端子，每个输出端子以有序阵列布置。 电路将每个输入端子电耦合到相应的输出端子，并且消除在相邻的连接器端子之间引起的串扰。 该电路包括在各对端子之间的四个导电路径。 第一和第三路径相对靠近并且与第二和第四路径基本间隔开。 第二和第四路径相对靠近。

公开(公告)号：US5997358A

公开(公告)日：1999-12-07

申请号：US923741

申请日：1997-09-02

Applicant: Luc Walter Adriaenssens ,  Amid Ihsan Hashim ,  Wayne David Larsen ,  Bryan Scott Moffitt ,  Julian Robert Pharney

Inventor： Luc Walter Adriaenssens ,  Amid Ihsan Hashim ,  Wayne David Larsen ,  Bryan Scott Moffitt ,  Julian Robert Pharney

IPC: H01R13/6466 ,  H01R13/6469 ,  H01R13/6473 ,  H01R24/00 ,  H01R24/64 ,  H05K1/02 ,  H05K1/16 ,  H01R23/02

CPC classification number: H05K1/0228 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/6473 ,  H01R24/64 ,  H05K1/0231 ,  H05K1/162 ,  H05K2201/09245 ,  H05K2201/10189 ,  Y10S439/941

Abstract: An electrical connector 60 achieves improved transmission performance by introducing predetermined amounts of compensation between two pairs of conductors that extend from its input terminals to its output terminals along interconnection paths. Electrical signals on one pair of conductors are coupled onto the other pair of conductors in two or more compensation stages that are time delayed with respect to each other. Illustratively, the electrical connector is a modular jack that is adapted to receive a modular plug 20. Associated with the modular plug and the input of the modular jack there exists a known amount of offending crosstalk A.sub.0, which is approximately canceled by the two or more stages of compensating crosstalk. In a first stage, compensating crosstalk A.sub.1 is introduced between the pairs, and it has a first predetermined magnitude and phase at a given frequency. In a second stage, compensating crosstalk A.sub.2 is introduced between the pairs, and it has a second predetermined magnitude and phase at the given frequency. Multiple compensation stages are needed because, at high frequencies, compensating crosstalk cannot be introduced that is exactly 180 degrees out of phase with the offending crosstalk because of propagation delay. The electrical connector 60 is constructed using a multi-layer printed wiring board 600 having input and output terminals where connection to metallic wires is made. These terminals are interconnected on the printed wiring board by metallic paths that are arranged to provide multiple stages of compensating crosstalk. When the connector 60 is joined to a plug 20, the near-end crosstalk of the combined structure is extremely low at frequencies up to at least 200 MHz.

Abstract translation: 电连接器60通过在沿着互连路径从其输入端子延伸到其输出端子的两对导体之间引入预定量的补偿来实现改进的传输性能。 一对导体上的电信号在两个或更多个相对于彼此延时的补偿级中耦合到另一对导体上。 示例性地，电连接器是适于接收模块化插头20的模块化插座。与模块化插头和模块插座的输入相关联，存在已知量的违规串扰A0，其大致被两个或更多个 补偿串扰的阶段。 在第一级中，在对之间引入补偿串扰A1，并且其在给定频率具有第一预定幅度和相位。 在第二级中，在对之间引入补偿串扰A2，并且其在给定频率处具有第二预定幅度和相位。 需要多个补偿级，因为在高频下，由于传播延迟，不能引入与异常串扰正好180度异相的补偿串扰。 电连接器60使用具有与金属线连接的输入和输出端子的多层印刷线路板600构成。 这些端子通过设置成提供多级补偿串扰的金属路径在印刷线路板上互连。 当连接器60连接到插头20时，组合结构的近端串扰在高达至少200MHz的频率下极低。