公开(公告)号：US10074576B2

公开(公告)日：2018-09-11

申请号：US14632375

申请日：2015-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L21/8258 ,  H01L27/12 ,  H01L29/786 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided.The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor. The first transistor is a p-channel transistor, and a channel formation region is formed using silicon.

公开(公告)号：US20180197889A1

公开(公告)日：2018-07-12

申请号：US15911233

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L23/544

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US09990997B2

公开(公告)日：2018-06-05

申请号：US15296493

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Kiyoshi Kato

IPC: G11C16/04 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/12 ,  H01L29/792 ,  G11C11/403 ,  G11C11/4097

CPC classification number: G11C16/0433 ,  G11C11/403 ,  G11C11/4097 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/792

Abstract: The memory device includes a first transistor and a circuit. The circuit includes a second to a (2n+1)th transistor, a first to an n-th capacitor, a first wiring, and a first to an n-th retention node (n is an integer greater than or equal to 2). When n is 2, a memory cell MC[1] includes a transistor ROS[1], a transistor WOS[1], and a capacitor C[1] and a memory cell MC[2] includes a transistor ROS[2], a transistor WOS[2], and a capacitor C[2]. A back gate of the transistor WOS[1] and a back gate of the transistor WOS[2] are electrically connected to a wiring WBG. A bake gate of a first transistor, a back gate of the transistor ROS[1], and a back gate of the transistor ROS[2] are electrically connected to a wiring RBG.

公开(公告)号：US09978774B2

公开(公告)日：2018-05-22

申请号：US15420628

申请日：2017-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US09905557B2

公开(公告)日：2018-02-27

申请号：US14445515

申请日：2014-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito ,  Kiyoshi Kato ,  Atsuo Isobe

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/40 ,  H01L29/786 ,  H01L27/1156 ,  H01L27/12 ,  G11C16/04 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

Abstract: A connection electrode for connecting a transistor including a semiconductor material other than an oxide semiconductor to a transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode.

公开(公告)号：US09852787B2

公开(公告)日：2017-12-26

申请号：US15464395

申请日：2017-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C11/419 ,  G11C5/14 ,  G06F3/06 ,  G11C14/00

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

公开(公告)号：US09852778B2

公开(公告)日：2017-12-26

申请号：US15428207

申请日：2017-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: G11C5/06 ,  G11C11/419 ,  G11C7/10 ,  G11C5/10 ,  G11C11/24 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C5/10 ,  G11C5/06 ,  G11C7/14 ,  G11C11/24 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.

公开(公告)号：US09825037B2

公开(公告)日：2017-11-21

申请号：US15359873

申请日：2016-11-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C5/06 ,  H01L27/105 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/11526 ,  H01L29/66 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09819261B2

公开(公告)日：2017-11-14

申请号：US14062249

申请日：2013-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC: H02M3/156 ,  G05B19/048 ,  G06F1/32 ,  G01R19/00 ,  G05B15/02 ,  G08B26/00 ,  G08B29/18 ,  H04W4/04 ,  H04L12/28

CPC classification number: H02M3/156 ,  G01R19/00 ,  G05B15/02 ,  G05B19/048 ,  G05B2219/24024 ,  G06F1/32 ,  G08B26/007 ,  G08B29/181 ,  H04L12/2825 ,  H04W4/043 ,  Y02B90/241 ,  Y02D70/00 ,  Y02D70/144 ,  Y04S20/242 ,  Y04S20/32 ,  Y04S20/36

Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.

公开(公告)号：US09761611B2

公开(公告)日：2017-09-12

申请号：US15016451

申请日：2016-02-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/12 ,  H01L29/788 ,  H01L27/1156 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/1225 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/7869 ,  H01L29/788

Abstract: A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween.