公开(公告)号：US20080014436A1

公开(公告)日：2008-01-17

申请号：US11775326

申请日：2007-07-10

Applicant: Robert Nickerson ,  Brian Taggart ,  Hai Ding

Inventor： Robert Nickerson ,  Brian Taggart ,  Hai Ding

IPC: B23K1/06 ,  B32B7/04

CPC classification number: B23K20/004 ,  B23K2101/42 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49052 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  Y10T428/249921 ,  Y10T428/26 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A wire-bonding substrate includes a curvilinear wire-bond pad. The curvilinear wire-bond pad is used in reverse wire bonding to couple a die with the substrate. A curvilinear wire-bond pad is also disclosed that is located directly above the via in the substrate. A wire-bonding substrate includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the wire-bonding substrate. A package is includes a chip stack with a total die-side characteristic dimension, and a total substrate-side characteristic dimension that is smaller than the total die-side characteristic dimension. A computing system includes the curvilinear wire-bond pad.

Abstract translation: 引线键合衬底包括曲线性引线键合焊盘。 曲线引线接合焊盘用于反向引线接合以将管芯与衬底耦合。 还公开了一种曲线形接合焊盘，其位于衬底中的通孔的正上方。 引线键合衬底包括第一引线接合焊盘和布线键合衬底中的第一引线接合焊盘正下方的第一通孔。 封装包括具有总模侧特性尺寸的芯片堆叠，以及小于总模侧特征尺寸的总基板侧特征尺寸。 一种计算系统包括曲线性的接线焊盘。

公开(公告)号：US07302756B2

公开(公告)日：2007-12-04

申请号：US10612281

申请日：2003-06-30

Applicant: Brian Taggart ,  Ronald L. Spreitzer ,  Robert Nickerson

Inventor： Brian Taggart ,  Ronald L. Spreitzer ,  Robert Nickerson

IPC: H01K3/10

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H05K2201/096 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wire-bonding substrate includes a first wire-bond pad and a first via that is disposed directly below the first wire-bond pad in the in the wire-bonding substrate. A package includes a die that is coupled to the first wire-bonding pad. The package can include a larger substrate that is coupled to the wire-bonding substrate through an electrical connection such as a solder ball. A process of forming the wire-bonding substrate includes via formation to stop on the wire-bond pad. A method of assembling a microelectronic package includes coupling the die to the wire-bond pad. A computing system includes the wire-bonding substrate.

Abstract translation: 引线键合衬底包括第一引线接合焊盘和布线键合衬底中的第一引线接合焊盘正下方的第一通孔。 封装包括耦合到第一引线接合焊盘的裸片。 封装可以包括通过诸如焊球之类的电连接而与引线键合衬底耦合的较大衬底。 形成引线接合基板的工艺包括通孔形成以在引线接合焊盘上停止。 组装微电子封装的方法包括将管芯耦合到引线接合焊盘。 计算系统包括引线接合衬底。

公开(公告)号：US20060289981A1

公开(公告)日：2006-12-28

申请号：US11168784

申请日：2005-06-28

Applicant: Robert Nickerson ,  Brian Taggart ,  Ronald Spreitzer

Inventor： Robert Nickerson ,  Brian Taggart ,  Ronald Spreitzer

IPC: H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4917 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multilayer interconnection system which facilitates high pin count and low package height. In some embodiments, the package may be wired so that the memory may only be accessed through the logic.

Abstract translation: 逻辑和存储器可以一起封装在单个集成电路封装中，在一些实施例中，其具有高输入/输出引脚数和低堆栈高度。 在一些实施例中，逻辑可以堆叠在可以堆叠在柔性基板上的存储器的顶部上。 这样的基板可以容纳有助于高引脚数和低封装高度的多层互连系统。 在一些实施例中，封装可以被布线，使得只能通过逻辑访问存储器。

公开(公告)号：US20060033217A1

公开(公告)日：2006-02-16

申请号：US10915293

申请日：2004-08-10

Applicant: Brian Taggart ,  Robert Nickerson ,  Ronald Spreitzer

Inventor： Brian Taggart ,  Robert Nickerson ,  Ronald Spreitzer

IPC: H01L21/48 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip-chip is mounted on a flex substrate. A flip-chip is mounted on a flex substrate, and a wire-bond chip is mounted on the flip-chip. A packaged flip-chip die is coupled to the flex substrate. A computing system is also disclosed that includes the flip-chip on a flex substrate configuration.

Abstract translation: 倒装芯片安装在柔性基板上。 倒装芯片安装在柔性基板上，并且引线接合芯片安装在倒装芯片上。 封装的倒装芯片与柔性基板相连。 还公开了一种计算系统，其包括柔性基板配置上的倒装芯片。

公开(公告)号：US20050214978A1

公开(公告)日：2005-09-29

申请号：US10807830

申请日：2004-03-24

Applicant: Brian Taggart ,  Robert Nickerson ,  Ronald Spreitzer

Inventor： Brian Taggart ,  Robert Nickerson ,  Ronald Spreitzer

IPC: H01L21/20 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48997 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Buildup layers may be formed over a flexible substrate. A suitable cavity may be formed in the buildup layers and a silicon die may be positioned over the flexible substrate on a die attach formed within the cavity. As a result, a lower profile flexible substrate package is possible.

Abstract translation: 堆积层可以形成在柔性基底上。 可以在堆积层中形成合适的空腔，并且可以在形成在空腔内的管芯附着件上将硅管芯定位在柔性基板上方。 因此，可以使用下部轮廓的柔性衬底封装。

公开(公告)号：US20050133255A1

公开(公告)日：2005-06-23

申请号：US10746595

申请日：2003-12-23

Applicant: John Conner ,  Brian Taggart ,  Robert Nickerson

Inventor： John Conner ,  Brian Taggart ,  Robert Nickerson

IPC: H01L23/498 ,  H01L23/50 ,  H05K3/22 ,  H05K7/06 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K3/222 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Some embodiments of the invention effectively shield signal traces on a substrate without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention provide improved power delivery without impacting the signal trace routing on the metal layers of the substrate. Other embodiments of the invention are described in the claims.

Abstract translation: 本发明的一些实施例有效地屏蔽衬底上的信号迹线，而不会影响衬底的金属层上的信号迹线路由。 本发明的其它实施例提供了改进的功率传递，而不影响衬底的金属层上的信号迹线布线。 在权利要求中描述了本发明的其它实施例。

公开(公告)号：US07780058B2

公开(公告)日：2010-08-24

申请号：US12038809

申请日：2008-02-27

Applicant: Siuyoung Yao ,  Brian Taggart

Inventor： Siuyoung Yao ,  Brian Taggart

IPC: B23K35/14 ,  B23K31/02

CPC classification number: B23K1/00 ,  B23K3/063 ,  B23K35/0227 ,  B23K35/262 ,  B23K35/3006 ,  B23K35/362 ,  B23K35/365 ,  Y10T428/12222

Abstract: Improved solder and soldering methods are disclosed. In accordance with one technique, a solder having a plurality of individual wire strands braided together is used. In accordance with another technique, the braided solder comprises both the same solder composition and wire gauge in the individual solder wire strands. In accordance with another technique, the braided solder comprises at least two different solder compositions used in the individual solder wire strands. In accordance with another technique, the braided solder comprises at least two different wire gauges used in the individual solder wire strands. In accordance with another technique, the braided solder comprises at least one wire strand where the primary surface is coated with a thin layer of a noble metal. In accordance with another technique, the braided solder comprises at least one wire strand where flux material is present. In accordance with one soldering technique, a method of soldering is accomplished by melting a plurality of braided solder strands to join a plurality of metallic surfaces together.

Abstract translation: 公开了改进的焊料和焊接方法。 根据一种技术，使用具有编织在一起的多个单独的线股的焊料。 根据另一种技术，编织焊料包括单个焊丝股线中相同的焊料组成和线规。 根据另一种技术，编织焊料包括用于各个焊丝线中的至少两种不同的焊料组合物。 根据另一技术，编织焊料包括在单独的焊丝股线中使用的至少两种不同的线规。 根据另一种技术，编织焊料包括至少一根线股，其中主表面涂覆有贵金属的薄层。 根据另一种技术，编织焊料包括至少一根线束，其中存在焊剂材料。 根据一种焊接技术，焊接方法是通过熔化多个编织的焊料线来将多个金属表面结合在一起来实现的。

公开(公告)号：US20060123096A1

公开(公告)日：2006-06-08

申请号：US10904672

申请日：2004-11-22

Applicant: Brian Taggart

Inventor： Brian Taggart

IPC: G06F15/16

CPC classification number: H04L67/08 ,  H04L67/04 ,  H04L67/322 ,  H04L69/329

Abstract: A multi-core processor computer system is described. The computer system includes a wireless communicator that enables access from at least one remote access site comprised of hardware equipped with a wireless communicator. This remote access site may not include a processor as part of the hardware. This remote hardware can access the capabilities of the multi-core processor computer and the computing system via wireless communicators and can allocate a dedicated core within the multi-core processor to the remote user, thereby enabling parallel, independent access to the computing system that can be shared by at least one additional user. The number of remote users can be correlated to the number of cores residing in the multi-core processor computing system. A process of wireless communication between the remote access sites and the computing system to enable independent computing processing capability is also described.

Abstract translation: 描述了一种多核处理器计算机系统。 计算机系统包括无线通信器，其能够从至少一个由配备有无线通信器的硬件组成的远程接入站点进行访问。 该远程访问站点可能不包括处理器作为硬件的一部分。 该远程硬件可以经由无线通信器访问多核处理器计算机和计算系统的能力，并且可以将多核处理器内的专用核心分配给远程用户，从而实现对计算系统的并行独立访问， 由至少一个额外的用户共享。 远程用户的数量可以与驻留在多核处理器计算系统中的核心数量相关联。 还描述了远程访问站点和计算系统之间的无线通信过程以实现独立的计算处理能力。

公开(公告)号：US20050285260A1

公开(公告)日：2005-12-29

申请号：US10877586

申请日：2004-06-25

Applicant: Dale Hackitt ,  Robert Nickerson ,  Brian Taggart

Inventor： Dale Hackitt ,  Robert Nickerson ,  Brian Taggart

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the invention provide a microelectronic device having a heat spreader positioned between a chip and substrate to which the chip is electrically connected. For one embodiment of the invention, the heat spreader is a thermal slug having a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the chip.

Abstract translation: 本发明的实施例提供了一种微电子器件，其具有位于芯片与芯片电连接的芯片和衬底之间的散热器。 对于本发明的一个实施例，散热器是具有近似等于芯片的热膨胀系数的热膨胀系数的热塞。

公开(公告)号：US07372133B2

公开(公告)日：2008-05-13

申请号：US11292705

申请日：2005-12-01

Applicant: Saeed Shojaie ,  Brian Taggart ,  Dale Hackitt

Inventor： Saeed Shojaie ,  Brian Taggart ,  Dale Hackitt

IPC: H01L23/495 ,  H01L23/28 ,  H01L23/498 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L23/3107 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between the die and respective ones of the contact leads; an overmold encapsulating the die, the paddle portion, the contact leads and the wirebonds; and a stiffening element encapsulated in the overmold and unconnected to electrical pathways within the leadframe package.

Abstract translation: 一种形成引线框封装的方法，根据该方法形成的引线框封装以及结合引线框封装的系统。 引线框封装包括：金属化层，其包括桨状部分和包括接触引线的接触部分; 安装在所述桨部上的模具; 连接在管芯和相应的接触引线之间的引线; 封装模具，桨形部分，接触引线和引线键的包覆模制; 以及封装在包覆模制中且与引线框封装内的电路不连接的加强元件。