公开(公告)号：US08541262B2

公开(公告)日：2013-09-24

申请号：US12874816

申请日：2010-09-02

Applicant: Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

Inventor： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC: H01L23/50

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

公开(公告)号：US08158489B2

公开(公告)日：2012-04-17

申请号：US12751512

申请日：2010-03-31

Applicant: Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

Inventor： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC: H01L21/30

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/013

Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

Abstract translation: 集成电路结构包括半导体晶片，其包括从半导体晶片的边缘延伸到半导体晶片的第一凹口。 载体晶片安装在半导体晶片上。 载体晶片具有与第一凹口的至少一部分重叠的第二切口。 面向半导体晶片的载体晶片的一侧与载体晶片的边缘形成锐角。 载体晶片的电阻率低于约1×108欧姆 - 厘米。

公开(公告)号：US20100330798A1

公开(公告)日：2010-12-30

申请号：US12751512

申请日：2010-03-31

Applicant: Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

Inventor： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC: H01L21/768 ,  H01L21/77

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/013

Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

Abstract translation: 集成电路结构包括半导体晶片，其包括从半导体晶片的边缘延伸到半导体晶片的第一凹口。 载体晶片安装在半导体晶片上。 载体晶片具有与第一凹口的至少一部分重叠的第二切口。 面向半导体晶片的载体晶片的一侧与载体晶片的边缘形成锐角。 载体晶片的电阻率低于约1×108欧姆 - 厘米。

公开(公告)号：US20100102453A1

公开(公告)日：2010-04-29

申请号：US12259879

申请日：2008-10-28

Applicant: Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

Inventor： Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.

Abstract translation: 提出了一种制造叠层半导体衬底的系统，结构和方法。 第一基板包括第一侧和第二侧。 贯穿基板通孔（TSV）从第一基板的第一侧突出。 TSV的第一突出部分具有导电保护涂层，并且TSV的第二突出部分具有隔离衬垫。 该系统还包括在TSV的第一突出部分的导电保护涂层处将第二衬底与第一衬底结合的第二衬底和接合界面结构。

公开(公告)号：US07633165B2

公开(公告)日：2009-12-15

申请号：US12206349

申请日：2008-09-08

Applicant: Kuo-Ching Hsu ,  Chen-Shien Chen ,  Boe Su ,  Hon-Lin Huang

Inventor： Kuo-Ching Hsu ,  Chen-Shien Chen ,  Boe Su ,  Hon-Lin Huang

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.

Abstract translation: 本公开提供集成电路。 集成电路包括配置在半导体衬底中的穿硅通孔（TSV）沟槽; 形成在所述半导体衬底上的导电焊盘，所述导电焊盘与所述TSV沟槽相邻; 设置在所述导电焊盘和所述TSV沟槽中的氮化硅层; 设置在氮化硅层上的钛层; 设置在钛层上的氮化钛层; 以及设置在氮化钛层上的铜层。

公开(公告)号：US08461045B2

公开(公告)日：2013-06-11

申请号：US13050424

申请日：2011-03-17

Applicant: Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

Inventor： Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

IPC: H01L21/44 ,  H01L29/41 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/481 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.

Abstract translation: 集成电路结构包括具有正面和背面的半导体衬底。 穿透硅通孔（TSV）穿透半导体衬底，其中TSV具有延伸到半导体衬底背面的后端。 再分配线（RDL）形成在半导体衬底的背面上并连接到TSV的后端。 钝化层在RDL上方，其中在钝化层中形成有开口，其中RDL的顶表面的一部分和RDL的侧壁通过开口露出。 在开口处形成金属表面，并与RDL的顶表面和侧壁的部分接触。

公开(公告)号：US08101499B2

公开(公告)日：2012-01-24

申请号：US12751512

申请日：2010-03-31

Applicant: Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

Inventor： Hon-Lin Huang ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Chen-Shien Chen

IPC: H01L21/30

Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

公开(公告)号：US20100090319A1

公开(公告)日：2010-04-15

申请号：US12347742

申请日：2008-12-31

Applicant: Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

Inventor： Kuo-Ching Hsu ,  Chen-Shien Chen ,  Hon-Lin Huang

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L23/481 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.

Abstract translation: 集成电路结构包括具有正面和背面的半导体衬底。 穿透硅通孔（TSV）穿透半导体衬底，其中TSV具有延伸到半导体衬底背面的后端。 再分配线（RDL）形成在半导体衬底的背面上并连接到TSV的后端。 钝化层在RDL上方，其中在钝化层中形成有开口，其中RDL的顶表面的一部分和RDL的侧壁通过开口露出。 在开口处形成金属表面，并与RDL的顶表面和侧壁的部分接触。