公开(公告)号：US20080230912A1

公开(公告)日：2008-09-25

申请号：US12053478

申请日：2008-03-21

Applicant: In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

Inventor： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US20080180191A1

公开(公告)日：2008-07-31

申请号：US12006996

申请日：2008-01-08

Applicant: Duk-Yong Kim ,  Kyoung-Ho Lee ,  In-Young Lee

Inventor： Duk-Yong Kim ,  Kyoung-Ho Lee ,  In-Young Lee

IPC: H01P1/18

CPC classification number: H01P1/184

Abstract: A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal.

Abstract translation: 提供可变移相器。 在可变移相器中，作为电介质基板的固定基板被固定地安装在壳体中，并且在其一个表面上具有至少一个弧形的微带线。 作为电介质基板的旋转基板可旋转地安装在壳体中，与固定基板的另一表面接触，并且在其接触表面上具有槽线。 即使在旋转期间，微带线耦合也在微带线和槽线之间进行。 微带线的两端连接到可变移相器的输出端口，并且时隙线电连接到可变移相器的输入端口，用于接收输入信号。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US07015590B2

公开(公告)日：2006-03-21

申请号：US10825199

申请日：2004-04-16

Applicant: Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

Inventor： Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

IPC: H01L21/461 ,  H01L21/469

CPC classification number: H01L24/13 ,  B23K3/0607 ,  B23K3/0623 ,  H01L21/2885 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

Abstract translation: 在布置在半导体芯片上的接触焊盘和布置在安装基板上的球垫之间形成加强焊料凸块连接器结构。 半导体芯片包括从中间层的表面向上延伸的至少一个增强突起。 安装基板包括从球垫向上延伸的至少一个加强突起，来自芯片和基板的突起被嵌入在焊料凸块连接器内。 在一些构造中，来自接触垫和球垫的加强突起的尺寸和布置成具有重叠的下部。 这些重叠部分可采取各种各样的构造，其允许突起重叠而不彼此接触，包括针阵列以及周围和被包围的元件的组合。 在每种构造中，加强突起将倾向于抑制裂纹形成和/或裂纹扩展，从而提高可靠性。

公开(公告)号：US06616754B1

公开(公告)日：2003-09-09

申请号：US09719593

申请日：2000-12-12

Applicant: Young-Hoon Park ,  In-Young Lee ,  Jung-Heon Lee ,  Mi-Kyoung Kim ,  Kyung-Hee Jung

Inventor： Young-Hoon Park ,  In-Young Lee ,  Jung-Heon Lee ,  Mi-Kyoung Kim ,  Kyung-Hee Jung

IPC: C04B2410

CPC classification number: C04B24/38 ,  C04B40/0039 ,  C04B2103/0082 ,  C04B2111/00112 ,  C04B22/062

Abstract: The present invention relates to a segregation reducing agent consisting of curdlan and alkaline materials and a hydraulic composition containing the segragation reducing agent, particularly, the present invention relates to the segregation reducing agent prepared by alkalifying a curdlan-producing fermentation broth per se or a curdlan powder with an alkaline material, and also relates to hydraulic compositions, concrete and mortar, comprising the segregation educing agent. This segregation reducing agent can provide a great segregation reduction effect for hydraulic compositions even at its small amount as well as guarantee the strength, filling ability and fluidity.

Abstract translation: 本发明涉及由凝乳糖和碱性物质组成的偏析还原剂以及含有共缩合还原剂的水硬性组合物，特别是本发明涉及通过使产生凝乳糖的发酵液本身碱化或凝乳土制成的分离还原剂 具有碱性材料的粉末，还涉及包含偏析教育剂的水硬性组合物，混凝土和砂浆。 这种偏析还原剂即使在少量的水硬性组合物中也可以提供很大的偏析降低效果，并且保证强度，填充能力和流动性。

公开(公告)号：US06380128B1

公开(公告)日：2002-04-30

申请号：US09452278

申请日：1999-11-30

Applicant: Pyung Sam Ji ,  Hee Mun Eum ,  Jung Bin Lee ,  Dong Hwa Kim ,  In Young Lee ,  In Sik Nam ,  Sung Won Ham ,  Soo Tae Choo

Inventor： Pyung Sam Ji ,  Hee Mun Eum ,  Jung Bin Lee ,  Dong Hwa Kim ,  In Young Lee ,  In Sik Nam ,  Sung Won Ham ,  Soo Tae Choo

IPC: B01J2106

CPC classification number: B01J21/063 ,  B01D53/8628 ,  B01J23/02 ,  B01J23/22 ,  B01J35/10 ,  B01J37/0236

Abstract: Disclosed are a catalyst for removing NOx from flue gas and its preparation. The catalyst comprises vanadium pentoxide, and barium oxide or calcium oxide as active components on a titanium dioxide support and is prepared by uniformly dispersing the metal oxides on the surface of the titanium dioxide support. This support is prepared by sufficiently drying and calcining a metatitanate (TiO(OH)2)-predominating slurry which is obtained from the course of the production of titanium dioxide for pigment from ilmenite. The catalyst exbihits excellent NOx removal activity as well as high durability against SO2, so that it can remove NOx for relatively longer period of time without being deteriorated by the poisoning induced by SO2 and significantly contribute to the prevention of plugging and corrosion of the downstream of a SCR reactor system.

Abstract translation: 公开了一种从烟气中除去NOx的催化剂及其制备方法。 催化剂包含五氧化二钒，氧化钡或氧化钙作为二氧化钛载体上的活性组分，并通过将金属氧化物均匀分散在二氧化钛载体的表面上制备。 通过充分干燥和煅烧从钛铁矿的颜料生产二氧化钛的过程中获得的偏钛酸盐（TiO（OH）2） - 浆液制备该载体。 催化剂具有优异的NOx去除活性以及对SO2的高耐久性，因此可以在不会被SO2引起的中毒的情况下，将NOx除去较长的时间，而且可以有效地防止下游的堵塞和腐蚀 SCR反应器系统。

公开(公告)号：US06292304B1

公开(公告)日：2001-09-18

申请号：US09562030

申请日：2000-05-01

Applicant: Jideog Kim ,  In Young Lee ,  Sukhan Lee

Inventor： Jideog Kim ,  In Young Lee ,  Sukhan Lee

IPC: G02B2730

CPC classification number: G02B27/09

Abstract: An apparatus for generating an independent coherent beam array from a single light source, in which individual coherent beams are selectively activated. The independent coherent beam array generating apparatus, which ensures high-efficient independent coherent beams from a single light source, are implemented by using a phase grating and a spacial light modulator. The number of multiple beams to be used as a light source for high-density recording and reading can be adjusted by varying the design of the phase grating. Regardless of the number of light sources required in various applications, once the beam array generating apparatus is adopted to the applications, the desired function of the applications can be implemented at low cost.

Abstract translation: 用于从单个光源产生独立相干光束阵列的装置，其中各个相干光束被选择性地激活。 通过使用相位光栅和空间光调制器来实现确保来自单个光源的高效独立相干光束的独立相干光束阵列发生装置。 可以通过改变相位光栅的设计来调整要用作用于高密度记录和读取的光源的多个光束的数量。 不管在各种应用中所需的光源数量如何，一旦将光束阵列发生装置应用于应用，就可以以低成本实现所需的应用功能。

公开(公告)号：US08362012B2

公开(公告)日：2013-01-29

申请号：US12934638

申请日：2009-04-16

Applicant: Ji Duck Kim ,  Hong-Chul Yoon ,  Seong Hee Cho ,  Inwoo Kim ,  Min Jae Cho ,  In Young Lee ,  Hyae Jung Hyun ,  Eunkyung Park

Inventor： Ji Duck Kim ,  Hong-Chul Yoon ,  Seong Hee Cho ,  Inwoo Kim ,  Min Jae Cho ,  In Young Lee ,  Hyae Jung Hyun ,  Eunkyung Park

IPC: C07D413/14 ,  A61K31/538

CPC classification number: C07D413/14 ,  C07D413/04

Abstract: The present invention relates to a novel benzoxazine benzimidazole derivative of formula (1) as an antagonist against a vanilloid receptor-1, a pharmaceutical composition comprising the same as an active ingredient, and a use thereof. The benzoxazine benzimidazole derivative of the present invention may be useful for preventing or treating a disease associated with antagonistic activity of vanilloid receptor-1: wherein, R1, R2, R3, R3′, Q1, Q2, Q3 and Q4 have same meanings as defined in the specification.

Abstract translation: 本发明涉及作为对香草素受体-1的拮抗剂的式（1）的新的苯并恶嗪苯并咪唑衍生物，包含其作为活性成分的药物组合物及其用途。 本发明的苯并恶嗪苯并咪唑衍生物可用于预防或治疗与香草素受体-1的拮抗活性相关的疾病：其中，R1，R2，R3，R3'，Q1，Q2，Q3和Q4具有与定义相同的含义 在规范中。

公开(公告)号：US08324733B2

公开(公告)日：2012-12-04

申请号：US12728683

申请日：2010-03-22

Applicant: In Young Lee ,  Donghyeon Jang ,  Namseog Kim

Inventor： In Young Lee ,  Donghyeon Jang ,  Namseog Kim

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/73 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13009 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/17051 ,  H01L2224/17505 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor device and a method for fabricating the same, wherein a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings.

Abstract translation: 一种半导体器件及其制造方法，其中去除包括衬垫的衬底的一部分以形成通孔。 在基板上形成绝缘层。 去除绝缘层的一部分以形成露出焊盘部分的多个开口。 形成贯通电极以填充通孔并且通过多个开口中的一个电连接到焊盘。 垫的一部分由多个开口中的另一个开口暴露。

公开(公告)号：US20110097846A1

公开(公告)日：2011-04-28

申请号：US12817304

申请日：2010-06-17

Applicant: Son-Kwan HWANG ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

Inventor： Son-Kwan HWANG ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

IPC: H01L21/50 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/9201 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2224/05552

Abstract: A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.

Abstract translation: 一种半导体芯片，包括：具有前表面和后表面的基板，所述基板具有形成在所述前表面上的第一通孔和形成在所述后表面中的第二通孔，形成在所述基板上的第一导电塞，所述第一导电 所述插头包括形成在所述第一通孔中的第一部分和从所述基板的前表面突出的第二部分，以及形成在所述第一导电插塞上的第二导电插塞，所述第二导电插塞具有比所述第一通孔更小的横截面积 导电插头