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    Memory device having open bit line structure and method of sensing data therefrom
    11.
    发明申请
    Memory device having open bit line structure and method of sensing data therefrom 失效
    具有开放位线结构的存储器件和从其感测数据的方法

    公开(公告)号：US20070274122A1

    公开(公告)日：2007-11-29

    申请号：US11649273

    申请日：2007-01-04

    申请人： Su-A Kim ,  Ki-Whan Song

    发明人： Su-A Kim ,  Ki-Whan Song

    IPC分类号： G11C11/24

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/10897

    摘要： A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.

    摘要翻译： 存储器件包括多个存储器块。 每个存储块包括多个位线，多个字线，设置在位线和字线的交点处的多个存储单元; 多个电容器和多个读出放大器。 每个读出放大器具有第一输入和第二输入。 第一输入端连接到第一个存储器块的第一位线，并通过一个电容器耦合到第二个存储器块的第一位线。 输入的第二输入连接到第二存储器块的第二位线，并且经由电容器中的一个耦合到第一个存储器块的第二位线。

    Semiconductor memory device having column redundancy scheme to improve redundancy efficiency
    12.
    发明授权
    Semiconductor memory device having column redundancy scheme to improve redundancy efficiency 有权
    具有列冗余方案以提高冗余效率的半导体存储器件

    公开(公告)号：US06414896B1

    公开(公告)日：2002-07-02

    申请号：US09905376

    申请日：2001-07-13

    申请人： Su-a Kim ,  Byung-sick Moon

    发明人： Su-a Kim ,  Byung-sick Moon

    IPC分类号： G11C800

    CPC分类号： G11C29/808 ,  G11C29/846

    摘要： A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.

    摘要翻译： 具有用于提高冗余效率的列冗余方案的半导体存储器件包括子存储块，冗余存储块，分别与子存储块相关联的全局数据输入输出线，冗余全局数据输入输出线和开关。 每个子存储块具有多个存储单元。 冗余存储块具有多个冗余存储单元。 子存储器块的所选存储单元的数据被发送到相应的全局数据输入输出线。 冗余存储器块的所选择的冗余存储单元的数据被发送到冗余全局数据输入输出线。 如果连接到全局数据输入输出线的存储单元发生故障，则A开关将全局数据输入输出线切换到冗余全局数据输入输出线。

    Memory device capable of quickly repairing fail cell
    13.
    发明授权
    Memory device capable of quickly repairing fail cell 有权

    公开(公告)号：US10235258B2

    公开(公告)日：2019-03-19

    申请号：US14683705

    申请日：2015-04-10

    申请人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    发明人： Jong-pil Son ,  Chul-woo Park ,  Su-a Kim

    IPC分类号： G06F11/20 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G06F11/10 ,  G11C29/04

    摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 审中-公开
    具有冗余电池的半导体存储器件和系统

    公开(公告)号：US20130117636A1

    公开(公告)日：2013-05-09

    申请号：US13670822

    申请日：2012-11-07

    申请人： Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    发明人： Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    IPC分类号： G11C29/04 ,  G06F11/16

    CPC分类号： G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

    摘要： In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

    摘要翻译： 在一个实施例中，存储器件包括存储单元阵列，数据线选择电路和选择控制逻辑。 存储单元阵列具有至少第一存储单元组和冗余存储单元组。 第一存储单元组包括与第一数据线相关联的多个第一存储单元，并且冗余存储单元组包括与冗余数据线相关联的多个冗余存储单元。 所述选择控制逻辑被配置为检测所述第一存储器单元组中的有缺陷的存储单元是否被访问，并且被配置为控制所述数据线选择电路经由所述冗余数据线经由所述第一数据线的访问来替换访问，使得 第一存储单元组中的检测到的有缺陷的存储单元被多个冗余存储单元中的一个代替。

    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS
    19.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 审中-公开
    具有冗余电池的半导体存储器件和系统

    公开(公告)号：US20130117615A1

    公开(公告)日：2013-05-09

    申请号：US13671261

    申请日：2012-11-07

    申请人： Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    发明人： Su-a KIM ,  Dae-hyun KIM ,  Woo-jin LEE

    IPC分类号： G11C29/04

    CPC分类号： G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

    摘要： In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

    摘要翻译： 在一个实施例中，存储器件包括存储单元阵列，数据线选择电路和选择控制逻辑。 存储单元阵列具有至少第一存储单元组和冗余存储单元组。 第一存储单元组包括与第一数据线相关联的多个第一存储单元，并且冗余存储单元组包括与冗余数据线相关联的多个冗余存储单元。 所述选择控制逻辑被配置为检测所述第一存储器单元组中的有缺陷的存储单元是否被访问，并且被配置为控制所述数据线选择电路经由所述冗余数据线经由所述第一数据线的访问来替换访问，使得 第一存储单元组中的检测到的有缺陷的存储单元被多个冗余存储单元中的一个代替。

    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 有权
    具有冗余电池的半导体存储器件和系统

    公开(公告)号：US20130117602A1

    公开(公告)日：2013-05-09

    申请号：US13670792

    申请日：2012-11-07

    申请人： Su-a KIM ,  Young-soo SOHN ,  Dae-hyun KIM

    发明人： Su-a KIM ,  Young-soo SOHN ,  Dae-hyun KIM

    IPC分类号： G06F11/20 ,  G06F12/00

    CPC分类号： G11C29/04 ,  G11C7/1045 ,  G11C29/808 ,  G11C29/81 ,  G11C29/848

    摘要： In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.

    摘要翻译： 在一个实施例中，存储器件包括具有至少第一存储单元组，第二存储单元组和冗余存储单元组的存储单元阵列。 第一存储单元组包括与第一数据线相关联的多个第一存储器单元，第二存储单元组包括与第二数据线相关联的多个第二存储器单元，并且冗余存储单元组包括多个冗余存储器 与冗余数据线相关联的单元。 数据线选择电路被配置为在输入/输出节点与第一数据线，第二数据和冗余数据线之一之间提供数据路径。