公开(公告)号：US6078210A

公开(公告)日：2000-06-20

申请号：US172092

申请日：1998-10-14

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G05F1/56 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C16/06 ,  G11C29/06 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H02J3/38

CPC分类号： G01R31/3004

摘要： The present invention relates to an internal voltage generating circuit. The internal voltage generating circuit comprises a reference voltage generating circuit for generating a reference voltage, which does not depend on an external power supply; and a comparator including a first input terminal, to which the reference voltage is supplied, a second input terminal, for comparing the voltages of the first and second input terminals and generating an output voltage according to the difference thereof at the output terminal; and an impedance element, which is selectively inserted between the output terminal and the second input terminal of the comparator according to an operation mode. An internal power supply voltage, which has a constant voltage during normal operation and has an accurate higher voltage during acceleration test, can be generated at the output terminal by inserting or not inserting a suitable impedance element between the second input terminal and output terminal according to the operation mode. The above-described comparator can be realized by a common differential amplifying circuit, for example. Further, a reference voltage value at normal operation can be fine-tuned by subdividing the impedance element. In the same way, the voltage value at acceleration test can be also fine-tuned by subdividing the impedance element.

摘要翻译： 本发明涉及内部电压发生电路。 内部电压产生电路包括用于产生不依赖于外部电源的参考电压的参考电压产生电路; 以及比较器，包括提供参考电压的第一输入端，第二输入端，用于比较第一和第二输入端的电压，并根据输出端的差异产生输出电压; 以及阻抗元件，其根据操作模式选择性地插入在比较器的输出端子和第二输入端子之间。 根据本发明，可以在输出端子上插入或不插入合适的阻抗元件，在正常工作期间具有恒定电压并且在加速度测试期间具有准确的较高电压的内部电源电压 操作模式。 上述比较器例如可以由公共差分放大电路实现。 此外，正常工作时的参考电压值可通过细分阻抗元件进行微调。 以同样的方式，加速度测试时的电压值也可以通过细分阻抗元件进行微调。

公开(公告)号：US20110141795A1

公开(公告)日：2011-06-16

申请号：US13031080

申请日：2011-02-18

申请人： Yasurou MATSUZAKI ,  Takaaki SUZUKI ,  Masafumi YAMAZAKI ,  Kenichi KAWASAKI ,  Shinnosuke KAMATA ,  Ayako SATO ,  Masato MATSUMIYA

发明人： Yasurou MATSUZAKI ,  Takaaki SUZUKI ,  Masafumi YAMAZAKI ,  Kenichi KAWASAKI ,  Shinnosuke KAMATA ,  Ayako SATO ,  Masato MATSUMIYA

IPC分类号： G11C11/24 ,  G11C8/16 ,  G11C11/406

CPC分类号： G11C8/16 ,  G06F13/1605 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/24 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/409 ,  G11C11/4093 ,  G11C2207/107 ,  G11C2207/108

摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

摘要翻译： 半导体存储器件包括多个N个外部端口，每个N个外部端口接收命令;以及内部电路，其在输入到一个外部端口的命令的最小间隔期间执行至少N次访问操作。

公开(公告)号：US07349280B2

公开(公告)日：2008-03-25

申请号：US11790831

申请日：2007-04-27

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. When a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

摘要翻译： 一种需要刷新操作的存储器电路，第一电路与时钟信号同步地接收命令，并在内部生成第一内部命令，第二电路在内部在规定的刷新中产生第二内部命令，例如刷新命令 周期。 并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制 。 当产生刷新定时信号时，可以在外部命令操作之间中断刷新操作。

公开(公告)号：US20070195628A1

公开(公告)日：2007-08-23

申请号：US11790832

申请日：2007-04-27

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072 ,  G11C11/4094 ,  G11C2211/4061 ,  G11C2211/4065

摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

公开(公告)号：US20070153613A1

公开(公告)日：2007-07-05

申请号：US11715851

申请日：2007-03-09

申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

IPC分类号： G11C5/14

CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

公开(公告)号：US20050082684A1

公开(公告)日：2005-04-21

申请号：US11006664

申请日：2004-12-08

申请人： Kazuyuki Aiba ,  Akira Takashima ,  Kaname Ozawa ,  Tetsuya Hiraoka ,  Takaaki Suzuki ,  Yasurou Matsuzaki

发明人： Kazuyuki Aiba ,  Akira Takashima ,  Kaname Ozawa ,  Tetsuya Hiraoka ,  Takaaki Suzuki ,  Yasurou Matsuzaki

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/433 ,  H01L25/065 ,  H01L27/118 ,  H01L29/06 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L29/0657 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511

摘要： A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.

摘要翻译： 通过在其表面上形成的涂层材料将半导体芯片固定成大致圆柱形状的状态。 变形的半导体芯片倒装芯片连接到插入器并用密封树脂密封到插入器上。 焊球作为外部端子设置在插入器的另一侧。

公开(公告)号：US06774655B2

公开(公告)日：2004-08-10

申请号：US10622472

申请日：2003-07-21

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06724675B2

公开(公告)日：2004-04-20

申请号：US10352985

申请日：2003-01-29

申请人： Akihiro Funyu ,  Shinya Fujioka ,  Hitoshi Ikeda ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato ,  Yasurou Matsuzaki

发明人： Akihiro Funyu ,  Shinya Fujioka ,  Hitoshi Ikeda ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/1042 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072

摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.

摘要翻译： 为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

公开(公告)号：US06636444B2

公开(公告)日：2003-10-21

申请号：US10057976

申请日：2002-01-29

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C1604

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C8/06

摘要： A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

公开(公告)号：US06621283B1

公开(公告)日：2003-09-16

申请号：US09437221

申请日：1999-11-10

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。