公开(公告)号：US20180211836A1

公开(公告)日：2018-07-26

申请号：US15652736

申请日：2017-07-18

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Yi-Chiau HUANG ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/02532 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7378

Abstract: The present disclosure generally relates to a device having a thin, low-defect, fully-relaxed silicon germanium (SiGe) layer, and methods of manufacture thereof. The methods generally include depositing a silicon oxide layer on a silicon layer, patterning the silicon oxide layer, exposing the silicon oxide layer to an etchant to form one or more recesses in the silicon layer and one or more faceted silicon oxide caps, and epitaxially growing a silicon germanium layer in the one or more recesses and over an apex of the one or more faceted silicon oxide caps. The device generally includes a silicon layer having one or more recesses defining one or more vertical extensions, one or more faceted silicon oxide caps on the one or more vertical extensions, and a silicon germanium layer in the one or more recesses and extending over an apex of the one or more faceted silicon oxide caps.

公开(公告)号：US20180073162A1

公开(公告)日：2018-03-15

申请号：US15413534

申请日：2017-01-24

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: C30B25/08 ,  C30B25/12 ,  C30B25/10 ,  C30B25/14 ,  C30B29/40 ,  C23C16/30 ,  C23C16/48 ,  C23C16/56 ,  H01L21/67

CPC classification number: C30B25/08 ,  C23C16/301 ,  C23C16/4405 ,  C23C16/481 ,  C23C16/56 ,  C30B25/00 ,  C30B25/105 ,  C30B25/12 ,  C30B25/14 ,  C30B25/165 ,  C30B29/06 ,  C30B29/40 ,  C30B33/00 ,  C30B35/00 ,  H01L21/2252 ,  H01L21/30 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67253

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

公开(公告)号：US20180033873A1

公开(公告)日：2018-02-01

申请号：US15617613

申请日：2017-06-08

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L29/045 ,  H01L29/66522 ,  H01L29/7853

Abstract: Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel.

公开(公告)号：US20180033872A1

公开(公告)日：2018-02-01

申请号：US15418128

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Errol Antonio C. SANCHEZ ,  Hua CHUNG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66795 ,  C23C16/45523 ,  C23C16/45525 ,  C30B25/025 ,  C30B25/04 ,  C30B25/165 ,  C30B25/186 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/24 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

公开(公告)号：US20170352557A1

公开(公告)日：2017-12-07

申请号：US15588641

申请日：2017-05-06

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO

IPC: H01L21/67 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/67017 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67201 ,  Y02P80/30

Abstract: Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.

公开(公告)号：US20170221706A1

公开(公告)日：2017-08-03

申请号：US15416287

申请日：2017-01-26

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO

IPC: H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/02546 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/02664 ,  H01L21/30621 ,  H01L21/3105 ,  H01L21/31122 ,  H01L29/66795

Abstract: A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.

公开(公告)号：US20160293384A1

公开(公告)日：2016-10-06

申请号：US14698556

申请日：2015-04-28

Applicant: APPLIED MATERIALS, INC.

Inventor： Chun YAN ,  Jim Zhongyi HE ,  Xinyu BAO ,  Teng-Fang KUO ,  Zhenwen DING ,  Adam LANE

IPC: H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32082 ,  H01J37/32862 ,  H01L21/02057 ,  H01L21/02068 ,  H01L21/02538 ,  H01L21/02661

Abstract: Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.

Abstract translation: 本文提供了从设置在基板处理系统中的表面去除污染物的方法。 在一些实施例中，用于从表面去除污染物的方法包括：向具有设置在处理室内的表面的处理室提供包含含氯气体，含氢气体和惰性气体的第一工艺气体; 点燃第一工艺气体以形成来自第一工艺气体的等离子体; 并将表面暴露于等离子体以从表面去除污染物。 在一些实施例中，表面是处理室部件的暴露表面。 在一些实施例中，表面是设置在诸如半导体晶片的衬底上的第一层的表面。

公开(公告)号：US20190172728A1

公开(公告)日：2019-06-06

申请号：US16172266

申请日：2018-10-26

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/673

Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

公开(公告)号：US20190169767A1

公开(公告)日：2019-06-06

申请号：US16266646

申请日：2019-02-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU

IPC: C30B25/08 ,  C30B35/00 ,  C30B29/40 ,  H01L21/67 ,  C30B25/16 ,  C30B25/00 ,  C23C16/48 ,  C23C16/56 ,  C30B33/00 ,  C23C16/30 ,  C30B25/10 ,  C30B25/12 ,  C30B25/14

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.

公开(公告)号：US20190035623A1

公开(公告)日：2019-01-31

申请号：US16148430

申请日：2018-10-01

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Melitta Manyin HON ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/66

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.