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23 条记录 (耗时 0.024 秒)

    Metal backed printed circuit board assemblies
    11.
    发明授权
    Metal backed printed circuit board assemblies 失效
    金属背衬印刷电路板组件

    公开(公告)号：US06734368B1

    公开(公告)日：2004-05-11

    申请号：US08890582

    申请日：1997-07-09

    申请人： Lisa J. Jimarez ,  David N. Light

    发明人： Lisa J. Jimarez ,  David N. Light

    IPC分类号： H05K103

    CPC分类号： H05K3/0061 ,  H05K3/321 ,  Y10T29/49124

    摘要： A method for conductively bonding a printed circuit board to a metal back plate is provided. The method includes the steps of providing a dielectric substrate that is metallized on its two faces; providing a metallic back plate; and bonding the metallic back plate to one of the metallized faces of the substrate using an electrically conductive adhesive that includes an adhesive polymer and at least one conductive metal having an electromagnetic force (EMF) that is equal to or less than one volt. The present invention also relates to a printed circuit board assembly which includes printed circuit board which includes a dielectric substrate having a first circuitized metallic layer disposed on one opposing face of the substrate and a second metallic layer disposed on the other opposing face of said substrate; a metal back plate; and an electrically conductive bonding layer disposed between the plate and the second metallic layer of the printed circuit board. The electrically conductive bonding layer contains an adhesive polymer and a conductive metal having an EMF that is less than one volt. The electrically conductive bonding layer is substantially free of silver.

    摘要翻译： 提供一种用于将印刷电路板导电地接合到金属背板的方法。 该方法包括以下步骤：提供在其两个表面上金属化的电介质基板; 提供金属背板; 以及使用包括粘合剂聚合物和至少一种具有等于或小于1伏的电磁力（EMF）的导电金属的导电粘合剂将所述金属背板接合到所述基板的金属化表面之一。 本发明还涉及一种印刷电路板组件，其包括印刷电路板，该印刷电路板包括具有设置在基板的一个相对面上的第一电路化金属层的电介质基板和设置在所述基板的另一相对面上的第二金属层; 金属背板 以及设置在印刷电路板的板和第二金属层之间的导电接合层。 导电接合层包含粘合剂聚合物和具有小于1伏特的EMF的导电金属。 导电接合层基本上不含银。

    I/C chip assembly
    12.
    发明授权
    I/C chip assembly 失效
    I / C芯片组装

    公开(公告)号：US06407334B1

    公开(公告)日：2002-06-18

    申请号：US09727271

    申请日：2000-11-30

    申请人： Lisa J. Jimarez ,  Miguel A. Jimarez

    发明人： Lisa J. Jimarez ,  Miguel A. Jimarez

    IPC分类号： H01L2302

    CPC分类号： H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

    摘要： A chip mounting assembly includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted on the substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed on the substrate. The stiffener has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad.

    摘要翻译： 芯片安装组件包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强件，其安装在基板上并与集成电路芯片横向间隔开。 在衬底上形成至少一个导电接地焊盘。 加强件在其中具有至少一个通孔，导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。

    Fixture for attaching a conformal chip carrier to a flip chip
    17.
    发明授权
    Fixture for attaching a conformal chip carrier to a flip chip 失效
    将保形芯片载体连接到倒装芯片的夹具

    公开(公告)号：US06337509B2

    公开(公告)日：2002-01-08

    申请号：US09116368

    申请日：1998-07-16

    申请人： David N. Cokely ,  Thomas M. Culnane ,  Lisa J. Jimarez ,  Miguel A. Jimarez ,  Li Li ,  Donald I. Mead

    发明人： David N. Cokely ,  Thomas M. Culnane ,  Lisa J. Jimarez ,  Miguel A. Jimarez ,  Li Li ,  Donald I. Mead

    IPC分类号： H01L23495

    CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75755 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014

    摘要： Fixtures for attaching a semiconductor chip to a substrate. The semiconductor chip has an array of joining material bumps, such as C4 solder balls. The substrate has an array of conductive pads corresponding to the array of joining material bumps. In a first embodiment the fixture has a body having a first cavity for containing the semiconductor chip and a second cavity in communication with the first cavity for containing the substrate. Whereby the substrate is placed over the semiconductor chip with the conductive pads opposing and in contact with the joining material bumps, such that during reflow of the joining material bumps, the weight of the substrate acts against the joining material bumps and aids in the attachment of the semiconductor chip to the substrate to form electrical connections therebetween. In a second embodiment the fixture has a first plate having a first opening for disposal of the semiconductor chip therein, a second plate stacked below the first plate and having a thickness substantially equal to the thickness of the substrate, the second plate further having a second opening opposing the first opening for disposal of the substrate therein, and a third plate stacked below the second plate such that the substrate is flattened in the second opening under the weight of the first plate thereby aiding in the attachment of the joining material bumps to their corresponding conductive pads during solder reflow to form electrical connections therebetween. Methods for use of the fixtures is also provided.

    摘要翻译： 用于将半导体芯片附接到基板的夹具。 半导体芯片具有连接材料凸块的阵列，例如C4焊球。 衬底具有对应于接合材料凸块阵列的导电焊盘阵列。 在第一实施例中，固定装置具有主体，该主体具有用于容纳半导体芯片的第一空腔和与第一空腔连通以容纳基板的第二空腔。 由此将衬底放置在半导体芯片上，其中导电焊盘与接合材料凸块相对并接触，使得在接合材料凸块的回流期间，衬底的重量抵抗接合材料凸起并且有助于附接 半导体芯片到基板以在它们之间形成电连接。 在第二实施例中，固定装置具有第一板，其具有用于在其中处理半导体芯片的第一开口，堆叠在第一板下方并且具有基本上等于衬底厚度的厚度的第二板，第二板还具有第二板 与第一开口相对地打开以处理其中的基板;以及第三板，堆叠在第二板下方，使得基板在第一板的重量下在第二开口中变平，由此辅助将接合材料凸块附接到它们 焊料回流期间相应的导电焊盘在其间形成电连接。 还提供了使用固定装置的方法。

    Reduction of chip carrier flexing during thermal cycling
    18.
    发明授权
    Reduction of chip carrier flexing during thermal cycling 有权
    在热循环期间减少芯片载体弯曲

    公开(公告)号：US06528179B1

    公开(公告)日：2003-03-04

    申请号：US09691935

    申请日：2000-10-19

    申请人： Lisa J. Jimarez ,  Miguel A. Jimarez

    发明人： Lisa J. Jimarez ,  Miguel A. Jimarez

    IPC分类号： H01L2912

    CPC分类号： H01L23/49822 ,  B32B15/08 ,  H01L23/142 ,  H01L2224/16225 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/125 ,  Y10T428/12528 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present. Since a propensity for cracking of the stiff chip carrier increases as the thermally induced displacement increases, the present invention, which avoids use of the stiffener ring, improves a structural integrity of the chip carrier.

    摘要翻译： 用于减少热循环期间芯片载体弯曲的方法和结构。 半导体芯片耦合到刚性芯片载体（即具有至少约3×10 5 psi的弹性模量的芯片载体），并且在芯片载体的外围没有加强环。 没有加强环，芯片载体响应于由于芯片和芯片载体之间的热膨胀系数不匹配而引起热应变的温度变化，能够经受自然弯曲（与受限制的弯曲相反）。 如果芯片载体上的温度从室温变化到约-40℃的温度，如果加强环不存在，则芯片载体的表面的最大热诱导位移比如下 存在加强环。 由于热引起的位移增加，刚性芯片载体的开裂倾向增加，所以避免使用加强环的本发明改善了芯片载体的结构完整性。

    Hybrid surface mount and pin thru hole circuit board
    19.
    发明授权
    Hybrid surface mount and pin thru hole circuit board 失效
    混合表面贴装和针孔通孔电路板

    公开(公告)号：US06521842B2

    公开(公告)日：2003-02-18

    申请号：US09885614

    申请日：2001-06-20

    申请人： Mark R. Brinthaupt, III ,  Lisa J. Jimarez ,  William F. Wildey

    发明人： Mark R. Brinthaupt, III ,  Lisa J. Jimarez ,  William F. Wildey

    IPC分类号： H05K100

    CPC分类号： H05K1/116 ,  H05K1/0201 ,  H05K3/3415 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/0969 ,  H05K2201/10189 ,  H05K2201/10659

    摘要： A multi-layer circuit board is disclosed. The circuit board comprises a plurality of conductive planes; a plurality of plated through hole sets, each set comprising one or more plated through holes, none to all of the plated through holes of each set contacting at least one the conductive plane; a thermal break formed around each plated through hole in each conductive plane to which the plated through hole is connected; and one or more thermal vents, in the vicinity of each plated through hole in each conductive plane to which the plated through hole is connected. Additionally, surface mount technology pads are provided on a top surface of the circuit board.

    摘要翻译： 公开了一种多层电路板。 电路板包括多个导电平面; 多个电镀通孔组，每组包括一个或多个电镀通孔，每组的电镀通孔中的至少一个接触至少一个导电平面; 在连接有电镀通孔的每个导电平面中的每个电镀通孔周围形成热断裂; 以及一个或多个热通风口，在每个电镀通孔附近，电镀通孔所连接的每个导电平面中。 此外，表面贴装技术垫设置在电路板的顶表面上。

    Surface metal balancing to reduce chip carrier flexing
    20.
    发明授权
    Surface metal balancing to reduce chip carrier flexing 失效
    表面金属平衡，减少芯片载体弯曲

    公开(公告)号：US06497943B1

    公开(公告)日：2002-12-24

    申请号：US09503395

    申请日：2000-02-14

    申请人： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Mark V. Pierson

    发明人： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Mark V. Pierson

    IPC分类号： B32B300

    CPC分类号： B32B15/08 ,  B32B15/20 ,  B32B17/10229 ,  B32B2250/40 ,  B32B2425/00 ,  H01L23/142 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01322 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing. A substrate, such as a chip carrier made of organic dielectric material, is formed and includes: internal circuitization layers, a plated through hole, and outer layers comprised of an allylated polyphenylene ether. A stiffener ring for mechanically stabilizing the substrate is bonded to an outer portion, such as an outer perimeter portion, of the top surface of the substrate, in light of the soft and conformal organic material of the substrate. The top and bottom surfaces of the substrate have metal structures, such as copper pads and copper circuitization, wherein a surface area (A) multiplied by a coefficient of thermal expansion (C) is greater for the metal structure at the bottom surface than for the metal structure at the top surface. A metal pattern is adjacent to the top surface so as to make the product AC of metal structures at or near the top and bottom surfaces approximately equal. The metal pattern reduces or eliminates flexing of the substrate in an elevated temperature environment, such as during a reflow of solder that couples a semiconductor chip to the substrate.

    摘要翻译： 用于芯片载体的表面金属平衡结构以及相关的制造方法，以减少或消除热诱导的芯片载体弯曲。 形成诸如由有机电介质材料制成的芯片载体的衬底，其包括：内部电路层，电镀通孔和由烯丙基化聚苯醚构成的外层。 根据衬底的软和保形有机材料，用于机械稳定衬底的加强环被结合到衬底的顶表面的外部部分，例如外周部分。 衬底的顶表面和底表面具有诸如铜焊盘和铜电路的金属结构，其中在底表面处的金属结构的表面积（A）乘以热膨胀系数（C）大于对于 金属结构在顶面。 金属图案与顶表面相邻，以使金属结构的产品AC在顶表面和底表面处或附近大致相等。 金属图案减少或消除了在升高的温度环境中的衬底的弯曲，例如在将半导体芯片耦合到衬底的焊料的回流期间。