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    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby
    12.
    发明授权
    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
    形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法

    公开(公告)号：US08232200B1

    公开(公告)日：2012-07-31

    申请号：US13051732

    申请日：2011-03-18

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    Method for removing copper oxide layer
    18.
    发明授权
    Method for removing copper oxide layer 失效
    去除氧化铜层的方法

    公开(公告)号：US08444868B2

    公开(公告)日：2013-05-21

    申请号：US12695273

    申请日：2010-01-28

    申请人： Tien-Jen Cheng ,  Stephan Grunow ,  Zhengwen Li ,  Huilong Zhu

    发明人： Tien-Jen Cheng ,  Stephan Grunow ,  Zhengwen Li ,  Huilong Zhu

    IPC分类号： C23F1/00

    CPC分类号： H01L21/02074 ,  C23G5/00

    摘要： The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.

    摘要翻译： 本发明涉及从铜表面去除氧化铜以提供清洁的铜表面的方法，其中所述方法包括将含有氧化铜的铜表面暴露于其中含有羧酸化合物的无水蒸气，其中无水蒸气为 由含有羧酸的无水有机溶液和选自烃和醚溶剂的一种或多种溶剂产生。

    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby
    19.
    发明授权
    Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed thereby 有权
    形成具有金属扩散阻挡层和由此形成的器件的具有镶嵌互连的集成电路器件的方法

    公开(公告)号：US08373273B2

    公开(公告)日：2013-02-12

    申请号：US13533135

    申请日：2012-06-26

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY
    20.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY 有权
    形成集成电路装置的方法，其具有金属扩散阻挡层和形成的器件的大分子互连

    公开(公告)号：US20120267785A1

    公开(公告)日：2012-10-25

    申请号：US13533135

    申请日：2012-06-26

    申请人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    发明人： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。