公开(公告)号：US06225687B1

公开(公告)日：2001-05-01

申请号：US09388768

申请日：1999-09-02

申请人： Dustin P. Wood

发明人： Dustin P. Wood

IPC分类号： H01L2316

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

摘要： A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

摘要翻译： 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。

公开(公告)号：US07687905B2

公开(公告)日：2010-03-30

申请号：US12039077

申请日：2008-02-28

申请人： Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

发明人： Brent S. Stone ,  Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC分类号： H01L23/34 ,  H01L21/02

CPC分类号： H01L23/50 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

摘要翻译： 集成电路封装包括由衬底的表面支撑的第一电容器和由衬底的表面支撑的第二电容器。 第一电容器在阴影区域内，第二电容器位于阴影阴影区域的外部。

公开(公告)号：US20080136010A1

公开(公告)日：2008-06-12

申请号：US12022254

申请日：2008-01-30

申请人： Dustin P. Wood ,  Kaladhar Radhakrishnan

发明人： Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC分类号： H01L23/495

CPC分类号： H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

摘要： An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

摘要翻译： 集成电路（IC）封装包括安装在基板的第一侧上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。

公开(公告)号：US07348214B2

公开(公告)日：2008-03-25

申请号：US11652425

申请日：2007-01-11

申请人： Dustin P. Wood ,  Kaladhar Radhakrishnan

发明人： Dustin P. Wood ,  Kaladhar Radhakrishnan

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

摘要： An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

摘要翻译： 集成电路（IC）封装包括安装在基板的第一面上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。

公开(公告)号：US07321172B2

公开(公告)日：2008-01-22

申请号：US11227532

申请日：2005-09-14

申请人： Dustin P. Wood ,  Debendra Mallik

发明人： Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US07265995B2

公开(公告)日：2007-09-04

申请号：US10747965

申请日：2003-12-29

申请人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

发明人： Kaladhar Radhakrishnan ,  Dustin P. Wood ,  Nicholas L. Holmberg

IPC分类号： H05K7/00

CPC分类号： H01G4/242 ,  H01G2/06 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L2224/16225 ,  H01L2924/14

摘要： An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

公开(公告)号：US07243423B2

公开(公告)日：2007-07-17

申请号：US11000255

申请日：2004-11-30

申请人： Dustin P. Wood

发明人： Dustin P. Wood

IPC分类号： H01R43/00

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

摘要： A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

摘要翻译： 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。

公开(公告)号：US07152313B2

公开(公告)日：2006-12-26

申请号：US10723414

申请日：2003-11-26

申请人： Dustin P. Wood ,  Mark E. Thurston ,  Mahadevan Suryakumar

发明人： Dustin P. Wood ,  Mark E. Thurston ,  Mahadevan Suryakumar

IPC分类号： H05K3/38

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/2072 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T156/1309 ,  H01L2924/00

摘要： In some embodiments, an article of manufacture includes a metal layer and a first dielectric layer in contact with a first face of the metal layer. The article of manufacture also includes a second dielectric layer in contact with a second face of the metal layer. The second face of the metal layer is opposite to the first face of the metal layer. The metal layer may be a continuous sheet having slots formed therein to allow the first and second dielectric layers to adhere to each other by way of the slots.

摘要翻译： 在一些实施例中，制品包括与金属层的第一面接触的金属层和第一电介质层。 制品还包括与金属层的第二面接触的第二电介质层。 金属层的第二面与金属层的第一面相反。 金属层可以是具有形成在其中的槽的连续片，以允许第一和第二电介质层通过槽彼此粘合。

公开(公告)号：US07656644B2

公开(公告)日：2010-02-02

申请号：US11972579

申请日：2008-01-10

申请人： Cengiz A. Palanduz ,  Dustin P. Wood

发明人： Cengiz A. Palanduz ,  Dustin P. Wood

IPC分类号： H01G4/228

CPC分类号： H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

摘要： A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.

摘要翻译： 一种方法，包括在衬底上沉积具有一定量的陶瓷材料的纳米颗粒的胶体的悬浮液; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括具有微处理器的计算设备的系统，所述微处理器通过衬底耦合到印刷电路板，所述衬底具有形成在表面上的至少一个电容器结构，所述电容器结构具有第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料具有柱状晶粒。

公开(公告)号：US07524754B2

公开(公告)日：2009-04-28

申请号：US11320314

申请日：2005-12-27

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin P. Wood

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

摘要翻译： 在本发明的一个实施例中，集成电路封装包括集成电路，封装基板，第一凸块，第二凸块和分流器，以提供电流分配和可靠性冗余。 第一和第二凸起在集成电路和封装衬底之间提供第一和第二电流通路。 分流器在第一凸块和第二凸块之间提供第三电流通路。