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    Predictive, adaptive power supply for an integrated circuit under test
    12.
    发明申请
    Predictive, adaptive power supply for an integrated circuit under test 有权
    用于被测集成电路的预测，自适应电源

    公开(公告)号：US20020186037A1

    公开(公告)日：2002-12-12

    申请号：US10206276

    申请日：2002-07-25

    Applicant: FormFactor, Inc.

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R031/26

    CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件（DUT）的电源端子。 在测试期间，DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘，作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化（噪声），辅助电源为电源输入端子提供额外的电流脉冲，以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数，以限制在DUT的功率输入端产生的电压变化。

    Tester channel to multiple IC terminals
    14.
    发明申请
    Tester channel to multiple IC terminals 有权

    公开(公告)号：US20040201391A1

    公开(公告)日：2004-10-14

    申请号：US10832899

    申请日：2004-04-27

    Applicant: FormFactor, Inc.

    Inventor： Charles A. Miller

    IPC: G01R001/00

    CPC classification number: G01R1/07378 ,  G01R3/00 ,  G01R31/2889 ,  G01R31/31723 ,  G01R31/318511 ,  G01R31/31905 ,  G01R31/31926 ,  Y10T29/49082 ,  Y10T29/49126 ,  Y10T29/4913

    Abstract: A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads. The tester channel measures the voltage of its input signal so that the logic state of the signals produced at each of the N IC output pads can be determined from the measured voltage.

    Predictive, adaptive power supply for an integrated circuit under test
    17.
    发明申请
    Predictive, adaptive power supply for an integrated circuit under test 失效
    用于被测集成电路的预测，自适应电源

    公开(公告)号：US20040075459A1

    公开(公告)日：2004-04-22

    申请号：US10725824

    申请日：2003-12-01

    Applicant: FORMFACTOR, INC.

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R031/26

    CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件（DUT）的电源端子。 在测试期间，DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘，作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化（噪声），辅助电源为电源输入端子提供额外的电流脉冲，以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数，以限制在DUT的功率输入端产生的电压变化。

    Closed-grid bus architecture for wafer interconnect structure
    18.
    发明申请
    Closed-grid bus architecture for wafer interconnect structure 有权

    公开(公告)号：US20030169061A1

    公开(公告)日：2003-09-11

    申请号：US10406669

    申请日：2003-04-02

    Applicant: FORMFACTOR, INC.

    Inventor： Charles A. Miller ,  John Matthew Long

    IPC: G01R031/02

    CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

    Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

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