公开(公告)号：US20160315182A1

公开(公告)日：2016-10-27

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160071932A1

公开(公告)日：2016-03-10

申请号：US14480974

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Kwan-Yong LIM ,  Sukwon HONG

IPC: H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.

公开(公告)号：US20180122644A1

公开(公告)日：2018-05-03

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Hoon KIM

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

公开(公告)号：US20180019337A1

公开(公告)日：2018-01-18

申请号：US15683228

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US20170309522A1

公开(公告)日：2017-10-26

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US20170271163A1

公开(公告)日：2017-09-21

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Kwan-Yong LIM

IPC: H01L21/3065 ,  H01L29/161 ,  H01L27/11 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US20160190255A1

公开(公告)日：2016-06-30

申请号：US15060052

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min Gyu SUNG

IPC: H01L29/10 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Abstract translation: 用于形成具有用于减少穿通漏电的封盖层的FinFET的方法包括提供具有设置在半导体衬底上的半导体衬底和鳍的中间半导体结构。 覆盖层设置在翅片上方，并且隔离填充物设置在覆盖层上。 去除隔离填充物和覆盖层的一部分以露出翅片的上表面部分。 突出层和鳍的下部限定了界面偶极层势垒，所述覆盖层的一部分可操作以提供增加的负电荷或增加与所述鳍相邻的正电荷，以减少与不具有 盖层。

公开(公告)号：US20160049401A1

公开(公告)日：2016-02-18

申请号：US14459005

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hiroaki NIIMI ,  Kwanyong LIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L29/06 ,  H01L27/11 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/28512 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: A non-planar semiconductor structure, for example, a dual FinFET structure, includes a n-type semiconductor device and a p-type semiconductor device. Metal-insulator-semiconductor (MIS) contacts provide electrical connection to the n-type device, and metal-semiconductor (MS) contacts provide electrical connection to the p-type device. The metal of both MIS and MS contacts is a same n-type work function metal. In one example, the semiconductor of the MIS contact includes epitaxial silicon germanium with a relatively low percentage of germanium, the insulator of the MIS contact includes titanium dioxide, the semiconductor for the MS contact includes silicon germanium with a relatively high percentage of germanium or pure germanium, and the metal for both contacts includes a n-type work function metal.

Abstract translation: 非平面半导体结构，例如双重FinFET结构，包括n型半导体器件和p型半导体器件。 金属绝缘体半导体（MIS）触点提供与n型器件的电连接，并且金属半导体（MS）触点提供与p型器件的电连接。 MIS和MS触点的金属都是相同的n型工作功能金属。 在一个示例中，MIS接触的半导体包括具有相对较低百分比的锗的外延硅锗，MIS接触的绝缘体包括二氧化钛，用于MS接触的半导体包括具有相对较高百分比的锗或纯度的硅锗 锗，并且用于两个触点的金属包括n型功函数金属。