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    Integrated circuits having gate cap protection and methods of forming the same
    11.
    发明授权
    Integrated circuits having gate cap protection and methods of forming the same 有权
    具有栅极盖保护的集成电路及其形成方法

    公开(公告)号：US09269611B2

    公开(公告)日：2016-02-23

    申请号：US14159944

    申请日：2014-01-21

    Applicant: GLOBALFOUNDRIES, Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

    IPC: H01L29/78 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

    Abstract translation: 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

    SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
    12.
    发明申请
    SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH 有权
    具有非常数PITCH的次平面半导体结构

    公开(公告)号：US20150380262A1

    公开(公告)日：2015-12-31

    申请号：US14843085

    申请日：2015-09-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC: H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

    Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

    Abstract translation: 公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。 形成多个翅片的方法包括形成具有第一间距的第一组翅片。 该方法还包括形成与第一组翅片相邻的翅片。 相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。 第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

    Dual epitaxy region integration
    13.
    发明授权
    Dual epitaxy region integration 有权
    双重外延区域整合

    公开(公告)号：US09224607B2

    公开(公告)日：2015-12-29

    申请号：US14029896

    申请日：2013-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    IPC: H01L27/146 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02

    CPC classification number: H01L21/28 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/66628

    Abstract: A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.

    Abstract translation: 半导体器件包括具有相反极性的第一器件区域和第二器件区域。 每个器件区域至少包括晶体管器件和相关联的外延。 形成高k屏障以仅覆盖第一器件区域外延。 高k屏障可以包括形成在第一器件区域外延的顶表面上的基本上水平的部分和形成在第一器件区域外延的外表面上的基本上垂直的部分。 基本上垂直的部分可以将第一器件区域与第二器件区域部分隔离。

    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES
    14.
    发明申请
    SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES 有权
    用于FINFET器件的自对准介电隔离

    公开(公告)号：US20150061040A1

    公开(公告)日：2015-03-05

    申请号：US14538401

    申请日：2014-11-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L27/088 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

    Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

    Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

    Prevention of fin erosion for semiconductor devices
    15.
    发明授权
    Prevention of fin erosion for semiconductor devices 有权
    防止半导体器件的翅片侵蚀

    公开(公告)号：US08809920B2

    公开(公告)日：2014-08-19

    申请号：US13670674

    申请日：2012-11-07

    Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/76

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Shallow trench isolation structures
    17.
    发明授权
    Shallow trench isolation structures 有权
    浅沟隔离结构

    公开(公告)号：US09548356B2

    公开(公告)日：2017-01-17

    申请号：US14714779

    申请日：2015-05-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

    IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

    Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

    Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

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