公开(公告)号：US10930750B2

公开(公告)日：2021-02-23

申请号：US16222911

申请日：2018-12-17

Applicant: IMEC vzw

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L39/14 ,  H01L29/43 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/41 ,  H01L29/76 ,  G06N10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3205 ,  H01L29/417 ,  H01L29/786

Abstract: The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

公开(公告)号：US10256157B2

公开(公告)日：2019-04-09

申请号：US15825826

申请日：2017-11-29

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/8258

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US10128371B2

公开(公告)日：2018-11-13

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/786

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US20170179281A1

公开(公告)日：2017-06-22

申请号：US15292778

申请日：2016-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/78642

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

公开(公告)号：US20190181050A1

公开(公告)日：2019-06-13

申请号：US16280428

申请日：2019-02-20

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/8238 ,  H01L29/786 ,  H01L21/8258 ,  H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L27/06 ,  H01L21/02

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US20180144935A1

公开(公告)日：2018-05-24

申请号：US15819226

申请日：2017-11-21

Applicant: IMEC VZW

Inventor： Salim El Kazzi ,  Clement Merckling

IPC: H01L21/02 ,  H01L21/687 ,  C30B29/46 ,  C30B23/02 ,  C30B23/06

CPC classification number: H01L21/02568 ,  C23C14/0026 ,  C23C14/0623 ,  C23C14/30 ,  C23C14/541 ,  C30B23/005 ,  C30B23/025 ,  C30B23/06 ,  C30B23/063 ,  C30B29/46 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02631 ,  H01L21/67248 ,  H01L21/68764

Abstract: A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

公开(公告)号：US20170178971A1

公开(公告)日：2017-06-22

申请号：US15352960

申请日：2016-11-16

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823807 ,  H01L21/02543 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US20150279947A1

公开(公告)日：2015-10-01

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。

公开(公告)号：US20170170313A1

公开(公告)日：2017-06-15

申请号：US15351504

申请日：2016-11-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Katia Devriendt ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  C30B29/40 ,  H01L21/02 ,  H01L29/66 ,  C30B25/04 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7827 ,  C30B25/04 ,  C30B29/06 ,  C30B29/08 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78642

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

公开(公告)号：US09601488B2

公开(公告)日：2017-03-21

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L27/088 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.