公开(公告)号：US08963321B2

公开(公告)日：2015-02-24

申请号：US13749006

申请日：2013-01-24

Applicant: Infineon Technologies AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/367 ,  H01L21/50 ,  H01L23/473 ,  H01L23/00 ,  H01L25/07 ,  H01L23/24 ,  H01L23/373 ,  H01L23/31 ,  H01L23/40

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。

公开(公告)号：US20140347818A1

公开(公告)日：2014-11-27

申请号：US14282556

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Andre Uhlemann ,  Thorsten Fath

IPC: H05K7/20 ,  H02M7/00

CPC classification number: H05K7/20927 ,  H01L23/3672 ,  H01L23/473 ,  H01L2924/0002 ,  H02M7/003 ,  Y10T29/41 ,  H01L2924/00

Abstract: A power semiconductor module includes a substrate and a two-part cooling system arranged under the substrate. The cooling system has upper and lower pieces. The upper piece forms a flow channel with the substrate for a cooling liquid. The upper piece has a first inflow and an outflow, through which the cooling liquid can be introduced into the flow channel and removed. The upper piece also has at least one second inflow, which is spaced apart from the first inflow in a longitudinal direction. The lower piece has an inlet and an outlet, the outlet being connected to the outflow and the inlet being connected to the first inflow. The lower piece also has a channel branching off from the inlet, which includes at least one bypass channel, which is connected to the second inflow, so part of the cooling liquid passes through the bypass channel into the flow channel.

Abstract translation: 功率半导体模块包括基板和布置在基板下方的两部分冷却系统。 冷却系统具有上下部件。 上部件与用于冷却液体的基板形成流动通道。 上部件具有第一流入和流出，冷却液可通过该第一流入和流出流入流动通道并被移除。 上部件还具有至少一个第二流入件，其沿着纵向方向与第一流入物间隔开。 下部件具有入口和出口，出口连接到流出口，入口连接到第一流入口。 下部件还具有从入口分支的通道，该通道包括至少一个旁通通道，其连接到第二流入口，因此部分冷却液体通过旁路通道进入流动通道。

公开(公告)号：US20140321063A1

公开(公告)日：2014-10-30

申请号：US13873599

申请日：2013-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andre Uhlemann ,  Alexander Herbrandt

IPC: H01L23/367 ,  B23K9/04 ,  H01L23/00

CPC classification number: B23K9/042 ,  B23K2101/40 ,  H01L21/4871 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor module includes a substrate having a metallized first side and a metallized second side opposing the metallized first side. A semiconductor die is attached to the metallized first side of the substrate. A plurality of cooling structures are welded to the metallized second side of the substrate. Each of the cooling structures includes a plurality of distinct weld beads disposed in a stacked arrangement extending away from the substrate. The substrate can be electrically conductive or insulating. Corresponding methods of manufacturing such semiconductor modules and substrates with such welded cooling structures are also provided.

Abstract translation: 半导体模块包括具有金属化第一侧和与金属化第一侧相对的金属化第二侧的衬底。 半导体管芯附着到衬底的金属化第一侧。 多个冷却结构被焊接到基板的金属化的第二侧。 每个冷却结构包括多个不同的焊接珠，其布置成离开基板延伸的堆叠布置。 衬底可以是导电的或绝缘的。 还提供了制造这种半导体模块和具有这种焊接冷却结构的基板的相应方法。

公开(公告)号：US11810889B2

公开(公告)日：2023-11-07

申请号：US17676350

申请日：2022-02-21

Applicant: Infineon Technologies AG

Inventor： Andre Uhlemann ,  Christoph Koch

IPC: H01L23/00

CPC classification number: H01L24/72

Abstract: An external contact element for a power semiconductor module includes a bonded blank strip, the bonded blank strip being formed such that the external contact element includes: a first contact portion configured to be coupled to the power semiconductor module by a first solder joint, a second contact portion spaced from the first contact portion in a thickness direction out of the plane of the first contact portion, the second contact portion being configured to be coupled to an external appliance, and a spring portion connecting the first and second contact portions to each other and configured to compensate a movement along the thickness direction. The bonded blank strip includes a first sheet of a first metal or first metal alloy and a second sheet of a different second metal or second metal alloy. The second sheet is omitted from at least a substantial part of the first contact portion.

公开(公告)号：US11778735B2

公开(公告)日：2023-10-03

申请号：US17683979

申请日：2022-03-01

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Mark Nils Muenzer ,  Andre Uhlemann

IPC: H05K1/02 ,  H05K1/18 ,  H01L23/473 ,  H01L23/44 ,  H05K7/20

CPC classification number: H05K1/0272 ,  H01L23/44 ,  H01L23/473 ,  H05K1/0203 ,  H05K1/185 ,  H05K7/20272 ,  H05K7/20927 ,  H05K2201/064 ,  H05K2201/09063 ,  H05K2201/10166

Abstract: A circuit board includes: an electrically insulating part and an electrically conductive part; at least one semiconductor chip embedded into the electrically insulating part in a part of the circuit board; and a cooling area above and below the at least one semiconductor chip. The electrically conductive part includes a first outer conductive layer on the first surface, a second outer conductive layer on the second surface, and a first inner conductive layer which is electrically connected to the semiconductor chip. The first inner conductive layer is electrically insulated from the first outer conductive layer and from the second outer conductive layer by the electrically insulating part in the cooling area, or is electrically connected to the first outer conductive layer outside the cooling area.

公开(公告)号：US11598904B2

公开(公告)日：2023-03-07

申请号：US16704873

申请日：2019-12-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Dirk Ahlers ,  Andreas Grassmann ,  Andre Uhlemann

IPC: G02B1/118 ,  H05K3/40 ,  H01L23/31 ,  H01L23/00 ,  H05K1/05 ,  H01L23/28 ,  H05K1/18 ,  H05K1/02 ,  H05K3/00

Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.

公开(公告)号：US20220183147A1

公开(公告)日：2022-06-09

申请号：US17683979

申请日：2022-03-01

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Mark Nils Muenzer ,  Andre Uhlemann

IPC: H05K1/02 ,  H01L23/473 ,  H05K1/18 ,  H05K7/20 ,  H01L23/44

Abstract: A circuit board includes: an electrically insulating part and an electrically conductive part; at least one semiconductor chip embedded into the electrically insulating part in a part of the circuit board; and a cooling area above and below the at least one semiconductor chip. The electrically conductive part includes a first outer conductive layer on the first surface, a second outer conductive layer on the second surface, and a first inner conductive layer which is electrically connected to the semiconductor chip. The first inner conductive layer is electrically insulated from the first outer conductive layer and from the second outer conductive layer by the electrically insulating part in the cooling area, or is electrically connected to the first outer conductive layer outside the cooling area.

公开(公告)号：US11266012B2

公开(公告)日：2022-03-01

申请号：US16711648

申请日：2019-12-12

Applicant: Infineon Technologies AG

Inventor： Tomas Manuel Reiter ,  Mark Nils Muenzer ,  Andre Uhlemann

IPC: H05K1/02 ,  H05K1/18 ,  H01L23/473 ,  H05K7/20 ,  H01L23/44

Abstract: A circuit board includes an electrically insulating part and an electrically conductive part. At least one semiconductor chip is embedded into the electrically insulating part in a part of the circuit board. Through openings in the part of the circuit board provide for passage of a cooling liquid. The through openings extend from a first surface of the circuit board to a second surface of the circuit board. The electrically conductive part includes a first outer conductive layer on the first surface and a second outer conductive layer on the second surface. The electrically conductive part also includes a first inner conductive layer which is electrically connected to the semiconductor chip. The first inner conductive layer is electrically insulated from the first outer conductive layer and from the second outer conductive layer by the electrically insulating part in the part of the circuit board.

公开(公告)号：US20160056088A1

公开(公告)日：2016-02-25

申请号：US14826629

申请日：2015-08-14

Applicant: Infineon Technologies AG

Inventor： Andre Uhlemann ,  Christoph Koch ,  Alexander Schwarz

IPC: H01L23/473 ,  H01L23/492 ,  H01L23/498 ,  B23K9/00 ,  B23K1/00 ,  B23K20/12 ,  B23K20/22 ,  B23K26/21 ,  B23K26/323 ,  H01L23/373 ,  B23K9/23

CPC classification number: H01L23/473 ,  B23K1/00 ,  B23K9/0026 ,  B23K9/232 ,  B23K20/129 ,  B23K20/22 ,  B23K26/21 ,  B23K26/323 ,  B23K2103/18 ,  H01L23/3736 ,  H01L23/4924 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cold plate includes a single piece member and a channel. A top side of the channel is open. A bottom side of the channel opposite the top side has an inlet and an outlet.

Abstract translation: 冷板包括单件件和通道。 频道的顶端是开放的。 通道的与顶侧相对的底侧具有入口和出口。

公开(公告)号：US20130134572A1

公开(公告)日：2013-05-30

申请号：US13749006

申请日：2013-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/367 ,  H01L21/50

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。