公开(公告)号：US20140284624A1

公开(公告)日：2014-09-25

申请号：US14207777

申请日：2014-03-13

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Juergen Hoegerl ,  Thilo Stolze

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L29/16

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/48 ,  H01L25/072 ,  H01L25/50 ,  H01L29/1608 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48491 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.

Abstract translation: 半导体部件包括具有与顶侧相对的顶侧和底侧的半导体本体。 顶部金属化被施加到顶侧，并且底部金属化被施加到底侧。 与顶部金属化和底部金属化相配合，防潮层完全密封半导体本体。

公开(公告)号：US11322451B2

公开(公告)日：2022-05-03

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US10211158B2

公开(公告)日：2019-02-19

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

公开(公告)号：US09859251B2

公开(公告)日：2018-01-02

申请号：US15012086

申请日：2016-02-01

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Peter Ossimitz

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/19104

Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

公开(公告)号：US09711462B2

公开(公告)日：2017-07-18

申请号：US13889370

申请日：2013-05-08

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Dominic Maier ,  Ulrich Wachter ,  Daniel Kehrer

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L23/52 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.

公开(公告)号：US20160313288A1

公开(公告)日：2016-10-27

申请号：US15136469

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Gottfried Beer ,  Sebastian Beer ,  Alfons Dehe ,  Franz Jost ,  Stefan Kolb ,  Guenther Ruhl ,  Rainer Markus Schaller

IPC: G01N29/24 ,  G01N29/02

CPC classification number: G01N29/2425 ,  G01N29/032 ,  G01N2291/021

Abstract: A photo-acoustic gas sensor includes a light emitter unit having a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and a wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit having a microphone. The light emitter unit is arranged so that the beam of light pulses traverses an area configured to accommodate the gas. The detector unit is arranged so that the microphone can receive a signal oscillating with the repetition frequency.

Abstract translation: 光声气体传感器包括光发射器单元，其具有光发射器，其被配置为发射具有预定重复频率和对应于待感测气体的吸收带的波长的光脉冲束，以及具有麦克风的检测器单元 。 光发射器单元布置成使得光束脉冲穿过配置成容纳气体的区域。 检测器单元布置成使得麦克风可以接收以重复频率振荡的信号。

公开(公告)号：US09331059B2

公开(公告)日：2016-05-03

申请号：US14101370

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Robert Allinger ,  Gottfried Beer ,  Juergen Hoegerl

IPC: H01L29/10 ,  H01L23/58 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  G01R31/28 ,  H01L27/02

CPC classification number: H01L25/18 ,  G01R31/2884 ,  H01L22/26 ,  H01L22/34 ,  H01L24/06 ,  H01L24/09 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06136 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2924/14252 ,  H01L2924/14253 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.

Abstract translation: 在各种实施例中，提供了用于芯片封装的芯片。 芯片可以包括衬底和衬底上的集成电路。 集成电路可以包括测试电路，例如内置的自检电路和操作电路，测试电路包括一个或多个第一驱动器级，每个具有第一驱动器性能，并且该操作电路包括一个或多个第二 驱动器级各自具有与第一驱动器性能不同的第二驱动器性能，第一触点与第一驱动级电耦合，以及与第二驱动级电耦合的第二触点，其中测试电路和第一触点被配置为提供 用于测试集成电路的测试模式，并且其中所述操作电路和所述第二触点被配置为提供与所述测试模式不同的所述集成电路的操作模式。

公开(公告)号：US09196510B2

公开(公告)日：2015-11-24

申请号：US14077694

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12043 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract translation: 半导体封装包括具有第一主面，与第一主面相对的第二主面和连接第一主面和第二主面的侧面的模体，包括多个第一半导体芯片的第一半导体模块和第一封装层 设置在第一半导体芯片上方，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个第二半导体沟道和设置在第二半导体沟道上方的第二封装层。 半导体封装还包括延伸穿过模具主体的一个或多个侧面的多个外部连接器。

公开(公告)号：US20150064846A1

公开(公告)日：2015-03-05

申请号：US14535591

申请日：2014-11-07

Applicant: Infineon Technologies AG

Inventor： Thomas Kilger ,  Ulrich Wachter ,  Dominic Maier ,  Gottfried Beer

IPC: H01L21/56 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L27/04 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 在半导体芯片的第二主面上施加第一封装层。 在第一半导体芯片的第一主面上施加电布线层。 将第二封装层施加在电布线层上。 第一封装层的厚度和第一半导体芯片的厚度减小。 可以将该结构单个化以获得多个半导体器件。

公开(公告)号：US08952521B2

公开(公告)日：2015-02-10

申请号：US13736553

申请日：2013-01-08

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Walter Hartner ,  Ottmar Geitner ,  Gottfried Beer ,  Klaus Pressel ,  Mehran Pour Mousavi

IPC: H01L23/04 ,  H01L23/66 ,  H01L21/768 ,  H01L23/498 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17519 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01Q23/00 ,  H01L2224/19 ,  H01L2924/014 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01064 ,  H01L2924/01044 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract translation: 在本发明的一个实施例中，半导体封装包括具有第一主表面和相对的第二主表面的衬底。 芯片设置在基板中。 芯片包括在第一主表面处的多个接触垫。 第一天线结构设置在第一主表面处。 反射器设置在第二主表面处。