公开(公告)号：US11581418B2

公开(公告)日：2023-02-14

申请号：US16894223

申请日：2020-06-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

公开(公告)号：US11342451B2

公开(公告)日：2022-05-24

申请号：US16697490

申请日：2019-11-27

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US10672686B2

公开(公告)日：2020-06-02

申请号：US16535237

申请日：2019-08-08

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417 ,  H01L29/78 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

公开(公告)号：US10304789B2

公开(公告)日：2019-05-28

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02 ,  H01L29/78 ,  H03F3/193 ,  H03F3/21 ,  H01L23/522

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US20180374921A1

公开(公告)日：2018-12-27

申请号：US16120855

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L29/205 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/304 ,  H01L21/762 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

公开(公告)号：US10020270B2

公开(公告)日：2018-07-10

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US09634085B1

公开(公告)日：2017-04-25

申请号：US15191854

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Christian Eckl

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

公开(公告)号：US20150243649A1

公开(公告)日：2015-08-27

申请号：US14186840

申请日：2014-02-21

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Matthias Zigldrum ,  Albert Birner ,  Richard Wilson ,  Saurabh Goel

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/4824 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/09 ,  H01L28/40 ,  H01L29/7802 ,  H01L29/7816 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/0912 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/1205 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/0001

Abstract: A power transistor die includes a transistor formed in a semiconductor body. The transistor has a gate terminal, an output terminal and a third terminal. The gate terminal controls a conduction channel between the output terminal and the third terminal. The power transistor die further includes a structured first metal layer disposed on and insulated from the semiconductor body. The structured first metal layer is connected to the output terminal of the transistor. The power transistor die also includes a first bond pad disposed on and insulated from the semiconductor body. The first bond pad forms an output terminal of the power transistor die and is capacitively coupled to the structured first metal layer so as to form a series capacitance between the output terminal of the transistor and the first bond pad. A power semiconductor package including the power transistor die is also provided.

Abstract translation: 功率晶体管管芯包括形成在半导体本体中的晶体管。 晶体管具有栅极端子，输出端子和第三端子。 栅极端子控制输出端子和第三端子之间的导通通道。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的结构化的第一金属层。 结构化的第一金属层连接到晶体管的输出端。 功率晶体管管芯还包括设置在半导体本体上并与半导体本体绝缘的第一接合焊盘。 第一接合焊盘形成功率晶体管管芯的输出端子，并且与结构化的第一金属层电容耦合，以便在晶体管的输出端和第一接合焊盘之间形成串联电容。 还提供了包括功率晶体管管芯的功率半导体封装。

公开(公告)号：US20240038848A1

公开(公告)日：2024-02-01

申请号：US18484966

申请日：2023-10-11

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Carsten Ahrens ,  Matthias Zigldrum

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L29/78 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.

公开(公告)号：US20240030334A1

公开(公告)日：2024-01-25

申请号：US18352572

申请日：2023-07-14

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Michaela Braun ,  Jan Ropohl ,  Matthias Zigldrum

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758

Abstract: In an embodiment, a Group III nitride-based semiconductor device includes: a multilayer Group III nitride-based structure including a first major surface; and a source electrode, a gate electrode and a drain electrode arranged on the first major surface. The gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure includes an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.