公开(公告)号：US20160301548A1

公开(公告)日：2016-10-13

申请号：US15187382

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Tawfiq Musah ,  Gokce Keskin ,  Ganesh Balamurugan ,  James E. Jaussi ,  Bryan K. Casper

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/03146 ,  H04L25/14

Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

公开(公告)号：US20150161005A1

公开(公告)日：2015-06-11

申请号：US14622776

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC: G06F11/10 ,  H03M13/15 ,  G11C5/02

CPC classification number: G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract translation: 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。

公开(公告)号：US12237589B2

公开(公告)日：2025-02-25

申请号：US17734529

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q5/47 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q9/04 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US11664568B2

公开(公告)日：2023-05-30

申请号：US16437245

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Cooper S. Levy ,  Chintan S. Thakkar ,  James E. Jaussi ,  Bryan K. Casper

IPC: H01P3/123 ,  H04B1/40 ,  H01P3/16 ,  H01P3/12

CPC classification number: H01P3/123 ,  H01P3/122 ,  H01P3/16 ,  H04B1/40

Abstract: Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.

公开(公告)号：US11126581B2

公开(公告)日：2021-09-21

申请号：US16882408

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Ganesh Balamurugan ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F1/18 ,  H04L25/02 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/36 ,  G06F13/20 ,  G06F13/42

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

公开(公告)号：US10437746B2

公开(公告)日：2019-10-08

申请号：US16028137

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall ,  Bryan K. Casper

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F11/10 ,  H04L25/49

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US10216680B2

公开(公告)日：2019-02-26

申请号：US15440568

申请日：2017-02-23

Applicant: Intel Corporation

Inventor： Tzu-Chien Hsueh ,  Ganesh Balamurugan ,  Bryan K. Casper

IPC: G06F13/40 ,  G06F13/36 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/18 ,  H04L25/02 ,  G06F13/20 ,  G06F13/42

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

公开(公告)号：US09929775B2

公开(公告)日：2018-03-27

申请号：US14668199

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Shreyas Sen ,  Chintan S. Thakkar ,  Bryan K. Casper ,  James E. Jaussi

IPC: H04B7/00 ,  H04B5/00 ,  H01P3/16 ,  H01Q13/24

CPC classification number: H04B5/0012 ,  H01P3/16 ,  H01Q13/24 ,  H04B5/0031

Abstract: Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

公开(公告)号：US09886343B2

公开(公告)日：2018-02-06

申请号：US14622776

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Bryan K. Casper ,  Stephen R. Mooney ,  David Dunning ,  Mozhgan Mansuri ,  James E. Jaussi

IPC: G06F11/10 ,  G11C5/02 ,  G11C29/12 ,  H03M13/15

CPC classification number: G06F11/1076 ,  G11C5/02 ,  G11C29/12 ,  H01L2224/16145 ,  H03M13/15 ,  H03M13/152

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

公开(公告)号：US20160352055A1

公开(公告)日：2016-12-01

申请号：US15152019

申请日：2016-05-11

Applicant: Intel Corporation

Inventor： James E. Jaussi ,  Stephen R. Mooney ,  Howard L. Heck ,  Bruce E. Pederson ,  Bryan K. Casper

IPC: H01R24/64 ,  H01R12/72

CPC classification number: H01R24/64 ,  H01R12/721 ,  H01R13/66 ,  H01R13/6658 ,  H01R24/28 ,  H01R24/62 ,  H01R2107/00

Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.

Abstract translation: 方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。