公开(公告)号：US20180150156A1

公开(公告)日：2018-05-31

申请号：US15879729

申请日：2018-01-25

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Teodora Ossiander ,  Andreas Wolter ,  Sonja Koller ,  Georg Seidemann ,  Jan Proschwitz ,  Hans-Joachim Barth ,  Bastiaan Elshof

IPC: G06F3/044 ,  G06F3/045 ,  G06F3/042 ,  G01L1/24 ,  G06F3/0354 ,  G06F3/038 ,  H04B1/3827 ,  G06F1/16

CPC classification number: G06F3/044 ,  G01L1/24 ,  G06F1/163 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04109 ,  H04B1/385

Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.

公开(公告)号：US09343389B2

公开(公告)日：2016-05-17

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L23/32 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US20150357311A1

公开(公告)日：2015-12-10

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US12191571B2

公开(公告)日：2025-01-07

申请号：US17323278

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Saravana Maruthamuthu ,  Bernd Waidhas ,  Andreas Augustin ,  Georg Seidemann

IPC: H01Q19/06 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01Q1/48 ,  H01Q15/08

Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

公开(公告)号：US11955462B2

公开(公告)日：2024-04-09

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20230317618A1

公开(公告)日：2023-10-05

申请号：US17707157

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/14 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L25/0655 ,  H01L23/49816

Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.

公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20220294115A1

公开(公告)日：2022-09-15

申请号：US17831151

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoecki ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US20220015244A1

公开(公告)日：2022-01-13

申请号：US17486462

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US11177220B2

公开(公告)日：2021-11-16

申请号：US16490521

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Andreas Wolter ,  Bernd Waidhas ,  Thomas Wagner

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.