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公开(公告)号:US20200211905A1
公开(公告)日:2020-07-02
申请号:US16236156
申请日:2018-12-28
Applicant: Intel Corporation
Inventor: Cheng-Ying HUANG , Willy RACHMADY , Gilbert DEWEY , Aaron LILAK , Kimin JUN , Brennen MUELLER , Ehren MANNEBACH , Anh PHAN , Patrick MORROW , Hui Jae YOO , Jack T. KAVALIEROS
IPC: H01L21/8238 , H01L27/092 , H01L29/423
Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.
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公开(公告)号:US20190267961A1
公开(公告)日:2019-08-29
申请号:US16348830
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Kevin LIN , Kimin JUN , Edris MOHAMMED
Abstract: The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.
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公开(公告)号:US20180219075A1
公开(公告)日:2018-08-02
申请号:US15747119
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: Patrick MORROW , Rishabh MEHANDRU , Aaron D. LILAK , Kimin JUN
IPC: H01L29/417 , H01L29/40 , H01L29/08 , H01L29/78 , H01L29/66
Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
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公开(公告)号:US20170077389A1
公开(公告)日:2017-03-16
申请号:US15122911
申请日:2014-06-16
Applicant: INTEL CORPORATION
Inventor: Donald W. NELSON , M Clair WEBB , Patrick MORROW , Kimin JUN
CPC classification number: H01L43/02 , H01L21/6835 , H01L23/49827 , H01L23/522 , H01L23/5389 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L27/0694 , H01L27/101 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12 , H01L2221/6835 , H01L2221/68363 , H01L2223/6677 , H01L2224/0401 , H01L2224/05548 , H01L2224/05568 , H01L2224/131 , H01L2224/16227 , H01L2224/94 , H01L2225/06517 , H01L2225/06572 , H01L2924/13091 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579 , H01L2224/03 , H01L2924/014 , H01L2924/00
Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.
Abstract translation: 一种方法,包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连,其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 其中。 一种装置,包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板,其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。
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公开(公告)号:US20240030188A1
公开(公告)日:2024-01-25
申请号:US18374972
申请日:2023-09-29
Applicant: Intel Corporation
Inventor: Anup PANCHOLI , Kimin JUN
IPC: H01L25/065 , H01L21/56 , H01L21/683 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L21/565 , H01L21/6835 , H01L24/92 , H01L24/73 , H01L25/50 , H01L2221/68372 , H01L2225/06513 , H01L2224/92133 , H01L2225/06586 , H01L2224/73209 , H01L2225/06524
Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
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公开(公告)号:US20230275135A1
公开(公告)日:2023-08-31
申请号:US18131336
申请日:2023-04-05
Applicant: Intel Corporation
Inventor: Patrick MORROW , Rishabh MEHANDRU , Aaron D. LILAK , Kimin JUN
IPC: H01L29/417 , H01L29/423 , H01L27/12 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L29/08 , H01L29/40
CPC classification number: H01L29/41791 , H01L21/823431 , H01L27/1266 , H01L29/78 , H01L29/401 , H01L29/785 , H01L29/0847 , H01L29/4236 , H01L29/6653 , H01L29/66553 , H01L29/66795 , H01L29/66803 , H01L21/2254 , H01L29/66545
Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
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公开(公告)号:US20220093683A1
公开(公告)日:2022-03-24
申请号:US17031719
申请日:2020-09-24
Applicant: Intel Corporation
Inventor: Han Wui THEN , Ibrahim BAN , Paul B. FISCHER , Kimin JUN , Paul NORDEEN , Pratik KOIRALA , Tushar TALUKDAR
Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 μm or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.
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18.
公开(公告)号:US20210057413A1
公开(公告)日:2021-02-25
申请号:US16954126
申请日:2018-03-28
Applicant: Gilbert DEWEY , Ravi PILLARISETTY , Jack T. KAVALIEROS , Aaron D. LILAK , Willy RACHMADY , Rishabh MEHANDRU , Kimin JUN , Anh PHAN , Hui Jae YOO , Patrick MORROW , Cheng-Ying HUANG , Matthew V. METZ , Intel Corporation
Inventor: Gilbert DEWEY , Ravi PILLARISETTY , Jack T. KAVALIEROS , Aaron D. LILAK , Willy RACHMADY , Rishabh MEHANDRU , Kimin JUN , Anh PHAN , Hui Jae YOO , Patrick MORROW , Cheng-Ying HUANG , Matthew V. METZ
IPC: H01L27/092 , H01L21/822 , H01L29/08 , H01L29/78 , H01L21/8238 , H01L27/06 , H01L29/66 , H01L29/06
Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.
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公开(公告)号:US20200035560A1
公开(公告)日:2020-01-30
申请号:US16316330
申请日:2017-08-25
Applicant: Intel Corporation
Inventor: Bruce BLOCK , Valluri R. RAO , Patrick MORROW , Rishabh MEHANDRU , Doug INGERLY , Kimin JUN , Kevin O'BRIEN , Patrick MORROW , Szyua S. LIAO
IPC: H01L21/822 , H01L29/04 , H01L29/08 , H01L23/528 , H01L23/00 , H01L29/16 , H01L29/20 , H01L27/092 , H01L27/12 , H01L23/532 , H01L21/8238 , H01L21/306 , H01L21/683 , H01L29/06 , H01L21/66
Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
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公开(公告)号:US20190122985A1
公开(公告)日:2019-04-25
申请号:US16227406
申请日:2018-12-20
Applicant: Intel Corporation
Inventor: Donald W. NELSON , Patrick MORROW , Kimin JUN
IPC: H01L23/528 , H01L23/00 , H01L21/768
Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.
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