公开(公告)号：US11854935B2

公开(公告)日：2023-12-26

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11622466B2

公开(公告)日：2023-04-04

申请号：US16902048

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Kyle Arrington ,  David Craig ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K7/14 ,  H05K7/20 ,  H01L23/22

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US11842944B2

公开(公告)日：2023-12-12

申请号：US16727770

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Frederick Atadana ,  Taylor Gaines ,  Minseok Ha

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/3675

Abstract: An integrated circuit (IC) assembly comprising an IC die and a frame material that has been dispensed over the assembly substrate to be further adjacent to a perimeter edge of the IC die. The frame material may be selected to have flow properties that minimize slump, for example so a profile of a transverse cross-section through the frame material may retain convex curvature. The frame material may be cured following dispense, and upon application of a thermal interface material (TIM), the frame material may and act as a barrier, impeding flow of the TIM. The frame material may be compressed by force applied through an external thermal solution, such as a heat sink, to ensure good contact to the TIM.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC: H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US20210327782A1

公开(公告)日：2021-10-21

申请号：US17359085

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Dong-Ho Han ,  Jaejin Lee ,  Jerrod Peterson ,  Kyle Arrington

IPC: H01L23/373 ,  H01L23/60 ,  H01L23/552 ,  H01L23/528

Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.

公开(公告)号：US20200350229A1

公开(公告)日：2020-11-05

申请号：US16398452

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Je-Young Chang ,  James C. Matayabas, JR. ,  Zhimin Wan ,  Kyle Arrington

IPC: H01L23/473 ,  H01L23/373 ,  H01L23/367 ,  H05K7/20

Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

公开(公告)号：US12238892B2

公开(公告)日：2025-02-25

申请号：US17128620

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Raanan Sover ,  James Williams ,  Bradley Smith ,  Nir Peled ,  Paul George ,  Jason Armstrong ,  Alexey Chinkov ,  Meir Cohen ,  Je-Young Chang ,  Kuang Liu ,  Ravindranath Mahajan ,  Kelly Lofgreen ,  Kyle Arrington ,  Michael Crocker ,  Sergio Antonio Chan Arguedas

IPC: H05K7/20

Abstract: A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment, the two-phase immersion cooling system may include a low boiling point liquid including at least two liquids that are substantially immiscible with one another.

公开(公告)号：US12046536B2

公开(公告)日：2024-07-23

申请号：US16398452

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Je-Young Chang ,  James C. Matayabas, Jr. ,  Zhimin Wan ,  Kyle Arrington

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/373 ,  H05K7/20

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L23/3733 ,  H05K7/20309 ,  H05K7/20327 ,  H05K7/20336

Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

公开(公告)号：US20240222345A1

公开(公告)日：2024-07-04

申请号：US18090707

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.