公开(公告)号：US09613934B2

公开(公告)日：2017-04-04

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  C09J9/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20150162313A1

公开(公告)日：2015-06-11

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及在集成电路（IC）封装组件中具有聚合物芯的互连结构的技术和配置。 在一个实施例中，一种装置包括具有设置在第一管芯的有源侧上的多个晶体管器件的第一管芯和与第一管芯电耦合的多个互连结构，其中多个互连结构中的各个互连结构具有 聚合物芯和设置在聚合物芯上的导电材料，所述导电材料被配置为在第一管芯的晶体管器件和第二管芯之间布置电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12199085B2

公开(公告)日：2025-01-14

申请号：US17716934

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US12170253B2

公开(公告)日：2024-12-17

申请号：US18114123

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US12119317B2

公开(公告)日：2024-10-15

申请号：US17032469

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/0823 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US20230197637A1

公开(公告)日：2023-06-22

申请号：US17554471

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mohammad Enamul Kabir ,  Nitin Deshpande ,  Omkar Karhade ,  Arnab Sarkar ,  Sairam Agraharam ,  Christopher Pelto ,  Gwang-Soo Kim ,  Ravindranath Mahajan

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L23/564 ,  H01L25/0655 ,  H01L21/447

Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

公开(公告)号：US20230197546A1

公开(公告)日：2023-06-22

申请号：US17557925

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Sairam Agraharam ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/56 ,  H01L2224/32145 ,  H01L2225/06517

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

公开(公告)号：US20210391295A1

公开(公告)日：2021-12-16

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11114388B2

公开(公告)日：2021-09-07

申请号：US16280993

申请日：2019-02-20

Applicant: INTEL CORPORATION

Inventor： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48

Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US20190371778A1

公开(公告)日：2019-12-05

申请号：US15996870

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J. De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.