公开(公告)号：US20210249322A1

公开(公告)日：2021-08-12

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US20250006643A1

公开(公告)日：2025-01-02

申请号：US18217049

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ram Viswanath ,  Xavier Brun

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

Abstract: Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.

公开(公告)号：US20240429199A1

公开(公告)日：2024-12-26

申请号：US18340635

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Yi Shi ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Xavier Brun ,  Johanna Swan

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68 ,  H01L21/683

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. Disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.

公开(公告)号：US12021016B2

公开(公告)日：2024-06-25

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Pooya Tadayon ,  Aastha Uppal ,  Weihua Tang ,  Paul Diglio ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/49833 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/5226

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US12002727B2

公开(公告)日：2024-06-04

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/3185 ,  H01L23/3675 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/35121

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US11978689B2

公开(公告)日：2024-05-07

申请号：US18089537

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L23/00 ,  H01L23/495 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20240063136A1

公开(公告)日：2024-02-22

申请号：US17891560

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Haris Khan Niazi ,  Yi Shi ,  Adel Elsherbini ,  Xavier Brun ,  Georgios Dogiamis ,  Thomas Brown ,  Omkar Karhade

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54473

Abstract: An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.

公开(公告)号：US09659889B2

公开(公告)日：2017-05-23

申请号：US14136908

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Mihir Oka ,  Xavier Brun ,  Dingying David Xu ,  Edward Prack ,  Kabirkumar Mirpuri ,  Saikumar Jayaraman

IPC: H01L23/00 ,  C08K3/36 ,  C08K3/22 ,  B23K1/20 ,  B23K1/00 ,  B23K26/362 ,  C09D179/02 ,  C08G73/02 ,  B23K101/42

CPC classification number: H01L24/11 ,  B23K1/0016 ,  B23K1/20 ,  B23K26/361 ,  B23K26/362 ,  B23K2101/42 ,  C08G73/0233 ,  C08K3/22 ,  C08K3/36 ,  C08K2003/2241 ,  C09D179/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  C08L79/04 ,  C08L79/02

Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.

公开(公告)号：US20160172229A1

公开(公告)日：2016-06-16

申请号：US14568552

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Arjun Krishnan ,  Mohit Mamodia ,  Dingying Xu

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/78 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Abstract translation: 一些示例性形式涉及用于晶片的加强带。 加强筋包括可拆卸地附接到安装带的安装带和加强件。 加强筋还包括附着在加强件上的管芯附着膜。 其他示例性形式涉及包括晶片和附接到晶片的加强筋的电子组件。 加强筋包括安装在晶片上的管芯附着膜。 加强件附接到管芯附着膜，并且安装带可拆卸地附接到加强件。 另一个示例形式涉及一种方法，其包括形成加强带，该加强带包括安装带，可移除地附接到安装带的加强件和附接到加强件的管芯附着膜。

公开(公告)号：US20250112181A1

公开(公告)日：2025-04-03

申请号：US18374522

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Yi Shi ,  Kimin Jun ,  Adel Elsherbini ,  Thomas Sounart ,  Wenhao Li ,  Xavier Brun

IPC: H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.