公开(公告)号：US10396022B2

公开(公告)日：2019-08-27

申请号：US16026824

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L21/48 ,  H01L23/498

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US10103054B2

公开(公告)日：2018-10-16

申请号：US13802011

申请日：2013-03-13

Applicant: INTEL CORPORATION

Inventor： Zhichao Zhang ,  Zhiguo Qian ,  Tolga Memioglu ,  Kemal Aygun

IPC: H05K7/10 ,  H05K7/12 ,  H01L21/768 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50

Abstract: Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

公开(公告)号：US10026682B2

公开(公告)日：2018-07-17

申请号：US15369659

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20170221727A9

公开(公告)日：2017-08-03

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US09589866B2

公开(公告)日：2017-03-07

申请号：US15046280

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L29/00 ,  H01L23/482 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160181189A1

公开(公告)日：2016-06-23

申请号：US14943880

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路（IC）组件中用于串扰缓解的地面通过群集的技术和配置。 在一些实施例中，IC封装组件可以包括被配置为在管芯和第二封装衬底之间路由输入/输出（I / O）信号和接地的第一封装衬底。 第一封装衬底可以包括设置在第一封装衬底的一侧上的多个触点和相同的通孔层的至少两个接地通孔，并且所述至少两个接地通孔可以形成一组接地通孔， 个人联系。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09232639B2

公开(公告)日：2016-01-05

申请号：US13707113

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 本文描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US12125777B2

公开(公告)日：2024-10-22

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gang Duan ,  Kemal Aygün ,  Jieying Kong ,  Brandon C. Marin

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US12033930B2

公开(公告)日：2024-07-09

申请号：US17033392

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Yiyang Zhou ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon Marin ,  Zhiguo Qian ,  Sarah Blythe ,  Bohan Shan ,  Jason Steill ,  Sri Chaitra Jyotsna Chavali ,  Leonel Arana ,  Dingying Xu ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/485 ,  H01L23/49827

Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

公开(公告)号：US11984439B2

公开(公告)日：2024-05-14

申请号：US16161578

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/0237

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.