公开(公告)号：US20240107900A1

公开(公告)日：2024-03-28

申请号：US17934212

申请日：2022-09-22

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Carl Radens ,  Ching-Tzu Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1675

Abstract: A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.

公开(公告)号：US20240081159A1

公开(公告)日：2024-03-07

申请号：US17929330

申请日：2022-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ching-Tzu Chen ,  Kevin W. Brew ,  JIN PING HAN ,  Timothy Mathew Philip ,  Injo Ok

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1608 ,  H01L45/1666

Abstract: A structure including alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A structure including horizontally aligned alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode. A method including forming alternating layers of phase change material layers and dielectric encapsulated heater element layers, the alternating layers of phase change material layers and the dielectric encapsulated heater element layers are sandwiched between a first electrode and a second electrode.

公开(公告)号：US11749602B2

公开(公告)日：2023-09-05

申请号：US16950453

申请日：2020-11-17

Applicant: International Business Machines Corporation

Inventor： Ching-Tzu Chen ,  Nicholas Anthony Lanzillo ,  Vijay Narayanan ,  Takeshi Nogami

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/3213 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5283

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

公开(公告)号：US09601685B1

公开(公告)日：2017-03-21

申请号：US15183172

申请日：2016-06-15

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L43/04 ,  H01L29/10 ,  H01L49/00 ,  H01L29/16 ,  H01L29/24 ,  H01L43/06 ,  G01N27/12 ,  H01L29/06 ,  H01L43/14

CPC classification number: H01L43/065 ,  G01N27/125 ,  H01L27/22 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/1606 ,  H01L29/24 ,  H01L43/02 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14 ,  H01L49/003

Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

公开(公告)号：US09484469B2

公开(公告)日：2016-11-01

申请号：US14571771

申请日：2014-12-16

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283 ,  H01L29/20 ,  H01L29/24 ,  H01L21/04 ,  H01L51/05 ,  H01L51/00 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L51/0541 ,  G01N27/414 ,  G01N27/4141 ,  G01N27/4146 ,  H01L21/02527 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/02606 ,  H01L21/043 ,  H01L21/283 ,  H01L21/441 ,  H01L21/7682 ,  H01L23/53276 ,  H01L28/60 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78684 ,  H01L29/78696 ,  H01L43/08 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2221/1094

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

Abstract translation: 本发明的实施例包括一种用于制造半导体器件的方法及其结果。 提供基板。 在基板上形成多个金属部分，其中多个金属部分被布置成使得基板的区域保持暴露。 在多个金属部分和基板的暴露区域上沉积薄膜层。 沉积介电层，其中电介质层与多个金属部分上的薄膜层的部分接触，并且其中介电层不与衬底的暴露区域上的薄膜层的部分接触 使得在衬底的暴露区域和电介质层之间的薄膜层之间存在一个或多个封闭空间。

公开(公告)号：US09406872B1

公开(公告)日：2016-08-02

申请号：US14941878

申请日：2015-11-16

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Ching-Tzu Chen ,  Joel D. Chudow

IPC: H01L43/06 ,  G01N27/12 ,  H01L43/04 ,  H01L43/14

CPC classification number: H01L43/065 ,  G01N27/125 ,  H01L27/22 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/1606 ,  H01L29/24 ,  H01L43/02 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14 ,  H01L49/003

Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

Abstract translation: 技术涉及半导体器件。 第一金属触点形成在基板的顶部。 第一金属触头沿第一方向布置，并且第一金属触点被布置成使得基板的区域保持暴露。 绝缘垫位于第一金属触点顶部的预定位置处，使得绝缘垫彼此间隔开。 第二金属触点形成在绝缘体焊盘的顶部上，使得第二金属触点沿与第一方向不同的第二方向布置。 第一和第二金属触点在预定位置处夹住绝缘体垫。 形成表面敏感导电通道以接触第一金属触点和第二金属触点。 四端子器件由接触一对第一金属触点并接触一对金属触点的表面敏感导电通道限定。

公开(公告)号：US20240324468A1

公开(公告)日：2024-09-26

申请号：US18124913

申请日：2023-03-22

Applicant: International Business Machines Corporation

Inventor： Ching-Tzu Chen ,  Henry K. Utomo

IPC: H10N50/10 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00

CPC classification number: H10N50/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22

Abstract: Spin-orbit torque magnetoresistive random access memory (SOT MRAM) devices are provided. Each of the SOT MRAM devices integrates a SOT layer and an interconnect layer at a same metal level using a topological conductor (i.e., a topological metal or a topological semimetal) as both the interconnect layer and the SOT layer. The SOT MRAM devices further include a magnetic tunnel junction (MTJ) structure contacting the SOT layer, and a contact structure contacting the MTJ structure.

公开(公告)号：US20240113024A1

公开(公告)日：2024-04-04

申请号：US17956334

申请日：2022-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ching-Tzu Chen ,  Christian Lavoie ,  Guy M. Cohen ,  Utkarsh Bajpai ,  Nicholas Anthony Lanzillo ,  Teodor Krassimirov Todorov ,  Oki GUNAWAN ,  NATHAN P. MARCHACK ,  Peter Kerns

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53209 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329

Abstract: An interconnect structure including conducting layers of topological semi-metals and/or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and/or topological insulators of the one or more conductive layers.

公开(公告)号：US11910731B2

公开(公告)日：2024-02-20

申请号：US17172118

申请日：2021-02-10

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Philip Joseph Oldiges ,  Robert L. Bruce ,  Ching-Tzu Chen

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/00 ,  H10N70/023 ,  H10N70/063 ,  H10N70/068 ,  H10N70/8413 ,  H10N70/8613 ,  H10N70/8833

Abstract: A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

公开(公告)号：US20230284541A1

公开(公告)日：2023-09-07

申请号：US17653143

申请日：2022-03-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  JIN PING HAN ,  Kevin W. Brew ,  Ching-Tzu Chen ,  Injo Ok

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/06 ,  H01L45/1293 ,  H01L45/1233 ,  H01L45/1608 ,  G11C13/004 ,  G11C13/0004 ,  G11C2013/0045

Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.