公开(公告)号：US10170608B2

公开(公告)日：2019-01-01

申请号：US14754751

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US20180331180A1

公开(公告)日：2018-11-15

申请号：US16042388

申请日：2018-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/775 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.

公开(公告)号：US20180308976A1

公开(公告)日：2018-10-25

申请号：US16011124

申请日：2018-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Isaac Lauer ,  Jiaxing Liu ,  Renee T. Mo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/306 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/845 ,  H01L29/1033 ,  H01L29/66568 ,  H01L29/66818 ,  H05K999/99

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

公开(公告)号：US10037885B2

公开(公告)日：2018-07-31

申请号：US15467555

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US20180096835A1

公开(公告)日：2018-04-05

申请号：US15832119

申请日：2017-12-05

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/775 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L29/786

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US20170125550A1

公开(公告)日：2017-05-04

申请号：US14924835

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/66

CPC classification number: H01L29/66795 ,  H01L22/30 ,  H01L22/34 ,  H01L29/66545

Abstract: A method for fabricating a test structure on a wafer includes forming a fin on a substrate, forming a first gate stack over the fin, the first gate stack having a first gate width, the first gate stack including a gate dielectric layer having a first thickness, forming a second gate stack over the fin, the second gate stack having a second gate width, the second gate stack including a gate dielectric layer having a second thickness, and forming a third gate stack over the fin, the third gate stack having a third gate width, the third gate stack including a gate dielectric layer having the second thickness, wherein the first gate stack is arranged a first distance from the second gate stack and the second gate stack is arranged the first distance from the third gate stack.

公开(公告)号：US09627378B2

公开(公告)日：2017-04-18

申请号：US14788297

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Robert H. Dennard ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

公开(公告)号：US20170084745A1

公开(公告)日：2017-03-23

申请号：US15365538

申请日：2016-11-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

公开(公告)号：US20170062476A1

公开(公告)日：2017-03-02

申请号：US15352085

申请日：2016-11-15

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/42388

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract translation: 在一个方面，形成CMOS器件的方法包括形成悬挂在BOX上的纳米线，其中第一/第二个或多个纳米线在BOX上的第一/第二悬架高度处悬挂，并且其中第一悬浮高度为 大于第二悬架高度; 在BOX上并围绕纳米线沉积共形栅极电介质，其中沉积在BOX上的共形栅极电介质是i）与保形栅极电介质沉积在第一个或多个纳米线周围的非接触位置，以及ii）是 与围绕第二个或多个纳米线沉积的共形栅极电介质直接物理接触，使得BOX在保形氧化物层在共形栅极电介质和第二个或多个之间的界面处生长期间用作氧源 纳米线。

公开(公告)号：US20170018508A1

公开(公告)日：2017-01-19

申请号：US14798007

申请日：2015-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L23/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.