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公开(公告)号：US20180007791A1
公开(公告)日：2018-01-04
申请号：US15702709
申请日：2017-09-12
Applicant: Intel Corporation
Inventor： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
IPC: H05K1/18 , H01L23/00 , H01L23/498 , H01R12/71 , H01R12/79
CPC classification number: H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
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公开(公告)号：US20160183375A1
公开(公告)日：2016-06-23
申请号：US14578037
申请日：2014-12-19
Applicant: Intel Corporation
Inventor： Vijaykumar Krithivasan , Jeffory L. Smalley , David J. Llapitan , Gaurav Chawla , Mani Prakash , Susan F. Smith
IPC: H05K1/18 , H01L23/40 , H01L23/498 , B23P15/26 , H01L21/48 , H05K3/32 , H05K7/20 , H01L23/367 , H01L21/50
CPC classification number: H05K7/2039 , H01L23/32 , H01L23/36 , H01L23/40 , H01L2924/0002 , H05K2201/10378 , H05K2201/1056 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例针对套接字加载元件和相关联的技术和配置。 在一个实施例中，设备可以包括加载元件，该加载元件被配置为将压缩负载从散热器传送到插座组件，其中所述加载元件构造成当所述加载元件与设置在 模具和插座组件，并且其中装载元件包括构造成容纳模具的开口。 可以描述和/或要求保护其他实施例。
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13.发明申请公开(公告)号：US20160118315A1
公开(公告)日：2016-04-28
申请号：US14918119
申请日：2015-10-20
Applicant: Intel Corporation
Inventor： Susan F. Smith , Jeffory L. Smalley , Mani Prakash , Thu Huynh
IPC: H01L23/367 , H01L25/065 , H01L21/48 , H01L25/00
CPC classification number: H01L23/3672 , H01L21/4882 , H01L23/40 , H01L23/4006 , H01L23/427 , H01L25/065 , H01L25/50 , H01L2023/4037 , H01L2023/4056 , H01L2023/4068 , H01L2924/0002 , H01L2924/00
Abstract: An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second heat exchanger disposed in the opening on the at least one secondary device; at least one heat pipe coupled to the first heat exchanger and the second heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including a first portion, a second portion and at least one heat pipe coupled to the first portion and the second portion; and coupling the heat exchanger to the multi-chip package.
Abstract translation: 一种装置，包括主要装置和至少一个辅助装置，其以平面阵列耦合到基板; 第一热交换器，其设置在所述主装置上并且在对应于所述至少一个次装置的区域上具有开口; 设置在所述至少一个次要装置的开口中的第二热交换器; 耦合到第一热交换器和第二热交换器的至少一个热管。 一种方法，包括将热交换器放置在多芯片封装上，所述热交换器包括耦合到所述第一部分和所述第二部分的第一部分，第二部分和至少一个热管; 并将热交换器耦合到多芯片封装。
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公开(公告)号：US20160093377A1
公开(公告)日：2016-03-31
申请号：US14498480
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Mani Prakash , Edward L. Payton , John K. Grooms , Dimitrios Ziakas , Mohammed Arafa , Raj K. Ramanujan , Dong Wang
IPC: G11C14/00 , G11C7/10 , G11C11/406
CPC classification number: G11C14/0018 , G11C5/04 , G11C7/1072 , G11C11/40615
Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了包括存储器模块的存储器模块，控制器和电子设备。 在一个实施例中，存储器模块包括非易失性存储器和到易失性存储器总线的接口，至少一个用于从主机平台接收电力的输入电源轨，以及控制器，其包括至少部分地包括硬件逻辑的逻辑，以将 从输入电源轨从输入电压到不同于输入电压的至少一个输出电压的电力。 还公开并要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US11587597B2
公开(公告)日：2023-02-21
申请号：US16911168
申请日：2020-06-24
Applicant: Intel Corporation
Inventor： Xiang Li , Phil Geng , George Vergis , Mani Prakash
Abstract: A connector includes mounting tabs that are extended relative to traditional mounting tabs. On a back side of the printed circuit board (PCB), the mounting tabs connect to a back plate. The mounting tabs extend through the PCB and connect with the back plate, which provides improved structural integrity. Depending on the connector, the use of the mounting tabs can use existing mounting holes for the connector and remove the need for additional mounting holes.
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公开(公告)号：US10163508B2
公开(公告)日：2018-12-25
申请号：US15055153
申请日：2016-02-26
Applicant: Intel Corporation
Inventor： Woojong Han , Mohamed Arafa , Brian S. Morris , Mani Prakash , James K. Pickett , John K. Grooms , Bruce Querbach , Edward L Payton , Dong Wang
Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180040536A1
公开(公告)日：2018-02-08
申请号：US15787544
申请日：2017-10-18
Applicant: Intel Corporation
Inventor： Jeffory L. Smalley , Susan F. Smith , Thu Huynh , Mani Prakash
IPC: H01L23/427 , H05K7/20 , H01L25/065 , H05K1/02 , H01L25/00
CPC classification number: H01L23/427 , H01L23/3672 , H01L23/473 , H01L24/00 , H01L25/0655 , H05K7/20336 , H05K7/20409 , H05K7/20509
Abstract: An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at least one secondary device, wherein the heat exchanger includes at least one portion disposed over an area corresponding to the primary device or the at least one second device including a deflectable surface; and at least one thermally conductive conduit coupled to the heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including the heat exchanger including at least one floating section operable to move in a direction toward or away from at least one of the plurality of dice and at least one thermally conductive conduit disposed in a channel of the heat exchanger and connected to the at least one floating section; and coupling the heat exchanger to the multi-chip package.
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公开(公告)号：US09848510B2
公开(公告)日：2017-12-19
申请号：US14578037
申请日：2014-12-19
Applicant: Intel Corporation
Inventor： Vijaykumar Krithivasan , Jeffory L. Smalley , David J. Llapitan , Gaurav Chawla , Mani Prakash , Susan F. Smith
CPC classification number: H05K7/2039 , H01L23/32 , H01L23/36 , H01L23/40 , H01L2924/0002 , H05K2201/10378 , H05K2201/1056 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
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公开(公告)号：US20170249991A1
公开(公告)日：2017-08-31
申请号：US15055153
申请日：2016-02-26
Applicant: Intel Corporation
Inventor： Woojong Han , Mohamed Arafa , Brian S. Morris , Mani Prakash , James K. Pickett , John K. Grooms , Bruce Querbach , Edward L Payton , Dong Wang
CPC classification number: G11C14/0009 , G11C5/02 , G11C5/025 , G11C5/141 , G11C11/005
Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
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