公开(公告)号：US20160315153A1

公开(公告)日：2016-10-27

申请号：US15197615

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/20 ,  H01L27/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L23/66 ,  H01L29/04 ,  H01L29/205

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20160079359A1

公开(公告)日：2016-03-17

申请号：US14946718

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/324 ,  H01L21/225 ,  H01L21/3213 ,  H01L21/31 ,  H01L21/311 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US10541305B2

公开(公告)日：2020-01-21

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/20 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US09865684B2

公开(公告)日：2018-01-09

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/308

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

公开(公告)号：US20170207310A1

公开(公告)日：2017-07-20

申请号：US15326022

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz Gardner ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/41783 ,  H01L21/28587 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.

公开(公告)号：US09691857B2

公开(公告)日：2017-06-27

申请号：US15197615

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/20 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US09048266B2

公开(公告)日：2015-06-02

申请号：US13956685

申请日：2013-08-01

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Robert Chau

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/36

CPC classification number: H01L29/66977 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/365 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/7781

Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US10263074B2

公开(公告)日：2019-04-16

申请号：US15605795

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US09847432B2

公开(公告)日：2017-12-19

申请号：US14912403

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz Gardner ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Robert Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/786 ,  H01L29/778 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/41 ,  H01L29/20

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78681

Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

公开(公告)号：US09837499B2

公开(公告)日：2017-12-05

申请号：US15326022

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz Gardner ,  Marko Radosavlijevic ,  Robert Chau

IPC: H01L29/15 ,  H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/28587 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.