公开(公告)号：US20130161824A1

公开(公告)日：2013-06-27

申请号：US13333395

申请日：2011-12-21

申请人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

发明人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

摘要翻译： 半导体器件具有形成为半导体晶片的多个导电通孔。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在每个导电通孔周围的半导体晶片中形成切口。 导电通孔周围的凹口可以通过湿蚀刻，干蚀刻或LDA形成。 第一绝缘层形成在半导体晶片和导电通孔的表面上并进入凹口中，以在导电通孔和半导体晶片之间提供应力消除。 去除第一绝缘层的一部分以露出导电通孔。 可以在导电通孔周围形成第一导电层和第二绝缘层。 可以在导电通孔上形成第二导电层。 凹口可以延伸到第二绝缘层中。

公开(公告)号：US07828707B2

公开(公告)日：2010-11-09

申请号：US11519908

申请日：2006-09-13

申请人： Chang Seung Lee ,  Kwang Choon Ro ,  Kae Dong Back ,  Kyu Ho Shin ,  Jong Kwang Kim ,  Won Kyoung Choi ,  Ki Deok Bae ,  Soon Cheol Kweon

发明人： Chang Seung Lee ,  Kwang Choon Ro ,  Kae Dong Back ,  Kyu Ho Shin ,  Jong Kwang Kim ,  Won Kyoung Choi ,  Ki Deok Bae ,  Soon Cheol Kweon

IPC分类号： B05C1/08 ,  B41J2/00

CPC分类号： G03G15/751 ,  Y10T29/49547

摘要： An image drum for selectively adsorbing toner in a printing apparatus is provided. A method and a configuration of ring electrodes formed on an outside of a drum body is also provided. That is, a control board is mounted inside the drum body, of which a plurality of terminals is externally exposed in the cylindrical drum body, and a photocurable resin is coated on the circumferential surface. Ring electrodes are then formed on circumferential surface of the drum body, by rotating the drum body and allowing an ultraviolet ray through the mask pattern onto the drum body to harden the liquid photocurable resin after contacting a mask-patterned mold mask to the circumferential surface of the drum body.

摘要翻译： 提供了一种用于在打印设备中选择性吸附调色剂的图像鼓。 还提供了形成在鼓体外侧的环形电极的方法和结构。 也就是说，控制板安装在鼓体内部，其中多个端子在圆筒形体中外露，并且光固化树脂涂覆在圆周表面上。 然后在鼓体的圆周表面上形成环形电极，通过旋转鼓本体，并使紫外线通过掩模图案转印到滚筒本体上，使得在将掩模图案化的掩模与掩模图案化的掩模接触之后使液体光固化树脂硬化 鼓体。

公开(公告)号：US07489327B2

公开(公告)日：2009-02-10

申请号：US11472319

申请日：2006-06-22

申请人： Soon Cheol Kweon ,  Kyu Ho Shin ,  Kae Dong Back ,  Chang Youl Moon ,  Ki Deok Bae ,  Won Kyoung Choi ,  Chang Seung Lee

发明人： Soon Cheol Kweon ,  Kyu Ho Shin ,  Kae Dong Back ,  Chang Youl Moon ,  Ki Deok Bae ,  Won Kyoung Choi ,  Chang Seung Lee

IPC分类号： B41J2/00 ,  B41J2/39 ,  B41J2/395

CPC分类号： G03G15/065 ,  G03G15/0815 ,  G03G2215/0634 ,  G03G2215/0646

摘要： An image forming apparatus that may be easily and inexpensively manufactured is provided. The image forming apparatus includes: a toner supply unit; an image forming element to which toner is adsorbed from the toner supply unit; an image developing unit disposed on an outer side of the image forming element, wherein said image developing unit selectively separates from the image forming element at least a part of the toner adsorbed to the image forming element in order to develop an image on the image forming element; and a toner return unit which returns the toner separated from the image forming element by the image developing unit to the toner supply unit.

摘要翻译： 提供了可以容易且廉价地制造的图像形成装置。 图像形成装置包括：调色剂供给单元; 调色剂从调色剂供给单元吸收到的图像形成元件; 设置在图像形成元件的外侧的图像显影单元，其中所述图像显影单元选择性地从图像形成元件分离吸附到图像形成元件的调色剂的至少一部分，以形成图像形成上的图像 元件; 以及调色剂返回单元，其将由图像显影单元从图像形成元件分离的调色剂返回到调色剂供应单元。

公开(公告)号：US20150311180A1

公开(公告)日：2015-10-29

申请号：US14791287

申请日：2015-07-03

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/528 ,  H01L23/48

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。

公开(公告)号：US08809191B2

公开(公告)日：2014-08-19

申请号：US13324446

申请日：2011-12-13

申请人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

发明人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.

摘要翻译： 半导体器件具有通过半导体管芯形成的多个导电通孔，其具有围绕导电通孔的第一绝缘层。 在LDA的导电通孔周围的第一绝缘层中形成凹部。 在第一绝缘层中形成凹陷之后，半导体晶片的一部分被LDA去除，使得导电通孔延伸到半导体晶片的表面之上。 第一绝缘层延伸到半导体晶片的表面或半导体晶片的表面之上。 第二绝缘层形成在半导体晶片的表面和导电通孔上。 第二绝缘层的第一部分被LDA去除，同时在第二绝缘层的第二部分围绕导电通孔留在半导体晶片的表面上。 在导电通孔上形成无电镀凸块。

公开(公告)号：US20130020713A1

公开(公告)日：2013-01-24

申请号：US13497611

申请日：2009-09-25

申请人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

发明人： Chirayarikathu Veedu Sankarapillai Premachandran ,  Rakesh Kumar ,  Nagarajan Ranganathan ,  Won Kyoung Choi ,  Ebin Liao ,  Yasuyuki Mitsuoka ,  Hiroshi Takahashi ,  Ryuta Mitsusue

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/6836 ,  B81B2207/092 ,  B81B2207/093 ,  B81B2207/097 ,  B81C2203/019 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In an embodiment, a wafer level package may be provided. The wafer level package may include a device wafer including a MEMS device, a cap wafer disposed over the device wafer, at least one first interconnect disposed between the device wafer and the cap wafer and configured to provide an electrical connection between the device wafer and the cap wafer, and a conformal sealing ring disposed between the device wafer and the cap wafer and configured to surround the at least one first interconnect and the MEMS device so as to provide a conformally sealed environment for the at least one first interconnect and the MEMS device, wherein the conformal sealing ring may be configured to conform to a respective suitable surface of the device wafer and the cap wafer when the device wafer may be bonded to the cap wafer. A method of forming a wafer level package may also be provided.

摘要翻译： 在一个实施例中，可以提供晶片级封装。 晶片级封装可以包括包括MEMS器件的器件晶片，设置在器件晶片上的帽晶片，设置在器件晶片和帽晶片之间的至少一个第一互连，并且被配置为在器件晶片和晶片级封装之间提供电连接 帽状晶片和保形密封环，其设置在器件晶片和盖晶片之间并且被配置为围绕至少一个第一互连和MEMS器件，以便为至少一个第一互连和MEMS器件提供保形密封的环境 ，其中所述保形密封环可以被配置为当所述器件晶片可以结合到所述盖晶片时，使其符合所述器件晶片和所述盖晶片的相应合适的表面。 还可以提供一种形成晶片级封装的方法。

公开(公告)号：US07784177B2

公开(公告)日：2010-08-31

申请号：US11447256

申请日：2006-06-06

申请人： Kae Dong Back ,  Ki Deok Bae ,  Chang Youl Moon ,  Kyu Ho Shin ,  Soon Cheol Kweon ,  Won Kyoung Choi ,  Chang Seung Lee

发明人： Kae Dong Back ,  Ki Deok Bae ,  Chang Youl Moon ,  Kyu Ho Shin ,  Soon Cheol Kweon ,  Won Kyoung Choi ,  Chang Seung Lee

IPC分类号： H05K3/02 ,  B41J2/39

CPC分类号： G03G15/348 ,  G03G2217/0075 ,  Y10T29/49117 ,  Y10T29/49155

摘要： An image drum manufacturing method including: providing a hollow cylindrical mold having a plurality of mold grooves circumferentially cut in its inner circumferential surface and a core portion having a smaller diameter than a hollow of the mold and having a slit-shaped combination groove; filling a conductive material into the mold grooves of the mold; inserting a control unit for individually applying a voltage to each terminal in the combination groove of the core portion, so that a conductive pattern corresponding to the conductive material is partially exposed; inserting the core portion into the mold so that the conductive pattern corresponds to the conductive material filled into each mold groove; and forming a drum body to be integrally formed with the control unit and the conductive material by filling a molten plastic into a space between the mold and the core portion.

摘要翻译： 一种图像鼓制造方法，包括：提供一种中空圆柱形模具，其具有在其内周面中周向切割的多个模具槽和具有比所述模具的中空部小的直径的芯部，并且具有狭缝状的组合槽; 将导电材料填充到模具的模具槽中; 插入用于单独向芯部的组合槽中的每个端子施加电压的控制单元，使得与导电材料相对应的导电图案部分地露出; 将芯部插入模具中，使得导电图案对应于填充到每个模具槽中的导电材料; 以及通过将熔融塑料填充到模具和芯部之间的空间中，形成与控制单元和导电材料一体形成的鼓体。

公开(公告)号：US09355993B2

公开(公告)日：2016-05-31

申请号：US14791287

申请日：2015-07-03

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

公开(公告)号：US09076724B1

公开(公告)日：2015-07-07

申请号：US14038275

申请日：2013-09-26

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。

公开(公告)号：US08742591B2

公开(公告)日：2014-06-03

申请号：US13333395

申请日：2011-12-21

申请人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

发明人： Won Kyoung Choi ,  Chang Bum Yong ,  Jae Hun Ku

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/481 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/01023 ,  H01L2224/05664 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

摘要翻译： 半导体器件具有形成为半导体晶片的多个导电通孔。 去除半导体晶片的一部分，使得导电通孔延伸到半导体晶片的表面之上。 在每个导电通孔周围的半导体晶片中形成切口。 导电通孔周围的凹口可以通过湿蚀刻，干蚀刻或LDA形成。 第一绝缘层形成在半导体晶片和导电通孔的表面上并进入凹口中，以在导电通孔和半导体晶片之间提供应力消除。 去除第一绝缘层的一部分以露出导电通孔。 可以在导电通孔周围形成第一导电层和第二绝缘层。 可以在导电通孔上形成第二导电层。 凹口可以延伸到第二绝缘层中。