公开(公告)号：US20150311180A1

公开(公告)日：2015-10-29

申请号：US14791287

申请日：2015-07-03

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/528 ,  H01L23/48

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。

公开(公告)号：US20120326296A1

公开(公告)日：2012-12-27

申请号：US13167487

申请日：2011-06-23

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/485 ,  H01L21/283

CPC分类号： H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

摘要翻译： 半导体器件具有半导体管芯，其具有形成在管芯上的第一导电层。 第一绝缘层形成在管芯上方，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 通过在第一绝缘层上形成第二绝缘层，其宽度小于第一开口的第二开口并将导电材料沉积到第二开口中来构造互连结构。 互连结构可以是导电柱或导电垫。 互连结构的宽度小于第一开口的宽度。 除去第一开口外部的第一绝缘层上的第二导电层，同时将第二导电层留在互连结构下。

公开(公告)号：US09355993B2

公开(公告)日：2016-05-31

申请号：US14791287

申请日：2015-07-03

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

公开(公告)号：US09076724B1

公开(公告)日：2015-07-07

申请号：US14038275

申请日：2013-09-26

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/94 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/8389 ,  H01L2224/94 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20106 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.

摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。

公开(公告)号：US20120326297A1

公开(公告)日：2012-12-27

申请号：US13167566

申请日：2011-06-23

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/283 ,  H01L23/485

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

摘要翻译： 半导体器件具有形成在半导体管芯上的第一导电层的半导体管芯。 第一绝缘层形成在半导体管芯上，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 互连结构形成在第二绝缘层的开口内的第一和第二导电层之上。 去除第二绝缘层。 互连结构可以是导电柱或导电垫。 凸起材料可以形成在导电柱上。 在导电柱或垫上方形成一层厚度小于1微米的保护涂层以减少氧化。 通过将导电柱或垫浸入含有锡或铟的浴中形成保护涂层。

公开(公告)号：US08587120B2

公开(公告)日：2013-11-19

申请号：US13167487

申请日：2011-06-23

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

公开(公告)号：US08435881B2

公开(公告)日：2013-05-07

申请号：US13167566

申请日：2011-06-23

申请人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

发明人： Won Kyoung Choi ,  Pandi Chelvam Marimuthu

IPC分类号： H01L21/283

CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11822 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

摘要翻译： 半导体器件具有形成在半导体管芯上的第一导电层的半导体管芯。 第一绝缘层形成在半导体管芯上，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 互连结构形成在第二绝缘层的开口内的第一和第二导电层之上。 去除第二绝缘层。 互连结构可以是导电柱或导电垫。 凸起材料可以形成在导电柱上。 在导电柱或垫上方形成一层厚度小于1微米的保护涂层以减少氧化。 通过将导电柱或垫浸入含有锡或铟的浴中形成保护涂层。

公开(公告)号：US08787950B2

公开(公告)日：2014-07-22

申请号：US13011123

申请日：2011-01-21

申请人： Won Kyoung Choi

发明人： Won Kyoung Choi

IPC分类号： H04W4/12

CPC分类号： H04W4/12 ,  H04L45/16 ,  H04L51/14 ,  H04L51/38 ,  H04W40/00

摘要： A mobile terminal and a method for transmitting a message thereof are provided. The method for transmitting a message in a mobile terminal including at least two communication units capable of communicating with different communication networks, includes, identifying circuits connected through the at least two communication units when at least two identification information of other mobile terminals to which the message is to be transmitted is input, and simultaneously transmitting the message to the at least two other mobile terminals according to the identification information through the identified circuits. Through the method, a message can be simultaneously transmitted to a plurality of other mobile terminals using characteristics of a multi-standby mobile terminal. In addition, the message transmission method can reduce a time required to transmit a message.

摘要翻译： 提供了一种用于发送其消息的移动终端和方法。 用于在包括能够与不同通信网络进行通信的至少两个通信单元的移动终端中发送消息的方法包括：当至少两个通信单元的至少两个识别信息与其中的消息 要被发送，并且通过所识别的电路根据识别信息同时将消息发送到至少两个其他移动终端。 通过该方法，可以使用多待机移动终端的特性将消息同时发送到多个其他移动终端。 此外，消息发送方法可以减少发送消息所需的时间。

公开(公告)号：US08380377B2

公开(公告)日：2013-02-19

申请号：US12730449

申请日：2010-03-24

申请人： Jong Kyung Lim ,  Byeong Seob Song ,  Hong Seok Song ,  Ki Jong Lee ,  Shin Hye Chun ,  Won Kyoung Choi ,  Hyong Joon Park ,  Joon Hwan Kim

发明人： Jong Kyung Lim ,  Byeong Seob Song ,  Hong Seok Song ,  Ki Jong Lee ,  Shin Hye Chun ,  Won Kyoung Choi ,  Hyong Joon Park ,  Joon Hwan Kim

IPC分类号： B60K6/22 ,  H02M7/48

CPC分类号： B60L1/003 ,  B60K6/48 ,  B60K2001/003 ,  B60K2001/005 ,  B60L3/003 ,  B60L2210/30 ,  B60L2210/40 ,  B60L2240/525 ,  Y02T10/6221 ,  Y02T10/7241 ,  Y02T90/16

摘要： A method for controlling a cooling system for controlling a power converter of a hybrid electric vehicle includes: estimating the temperature of a power converter at the time of a CAN communication error as a current temperature of the power converter and controlling a cooling system at a cooling rate based on the estimated temperature; and controlling the cooling rate of the cooling system depending on whether an output of the power converter is greater than a reference value. According to the method, the cooling system can be more effectively controlled.

摘要翻译： 一种用于控制用于控制混合电动车辆的功率转换器的冷却系统的方法，包括：将CAN通信错误时的功率转换器的温度估计为功率转换器的当前温度并控制冷却系统的冷却 基于估计温度的速率; 以及根据所述功率转换器的输出是否大于参考值来控制所述冷却系统的冷却速率。 根据该方法，可以更有效地控制冷却系统。

公开(公告)号：US09559004B2

公开(公告)日：2017-01-31

申请号：US13469754

申请日：2012-05-11

申请人： Byung Joon Han ,  Il Kwon Shim ,  Won Kyoung Choi

发明人： Byung Joon Han ,  Il Kwon Shim ,  Won Kyoung Choi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01L21/6836 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81903 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions.

摘要翻译： 半导体器件包括载体，载体包括设置在载体上的粘合剂。 半导体器件还包括半导体晶片，其包括由非有源区分隔的多个半导体管芯。 在半导体管芯上形成多个凸点。 半导体晶片被安装到载体上，粘合剂设置在多个凸起周围。 照射能量被施加到非有源区域以在非活性区域内形成修饰区域。 半导体晶片沿着改质区域分割成半导体管芯。 通过向半导体晶片施加应力，沿着改质区域将半导体晶片分离。 在分离半导体晶片之后，从多个凸起周围除去粘合剂。 半导体晶片包括通过硅通孔的多个半导体管芯。 修改区域可选地包括多个垂直堆叠的改性区域。