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11.发明授权Photoelectric device using PN diode and silicon integrated circuit (IC) including the photoelectric device 失效光电器件采用PN二极管和硅集成电路（IC），包括光电器件公开(公告)号：US08346026B2
公开(公告)日：2013-01-01
申请号：US12517802
申请日：2007-08-07
Applicant: Jeong-Woo Park , Gyungock Kim , Young-Ahn Leem , Hyun-Soo Kim , Bongki Mheen
Inventor： Jeong-Woo Park , Gyungock Kim , Young-Ahn Leem , Hyun-Soo Kim , Bongki Mheen
CPC classification number: H01L31/12 , H01L27/144
Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.
Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路（IC）。 光电装置包括：基板; 以及在所述衬底上形成为PN二极管的光波导，其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极，其中PN二极管的N型和P型半导体以高浓度掺杂，并且N型半导体的掺杂浓度高于或等于P 型半导体。
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公开(公告)号：US20110259627A1
公开(公告)日：2011-10-27
申请号：US13067883
申请日：2011-07-01
Applicant: Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
Inventor： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.
Abstract translation: 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。
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公开(公告)号：US07928442B2
公开(公告)日：2011-04-19
申请号：US12441381
申请日：2007-08-17
Applicant: Bongki Mheen , Jeong-Woo Park , Hyun-Soo Kim , Gyungock Kim
Inventor： Bongki Mheen , Jeong-Woo Park , Hyun-Soo Kim , Gyungock Kim
IPC: H01L31/036
CPC classification number: G02F1/025 , G02F1/2257 , H01L33/0037
Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.
Abstract translation: 提供了具有应变埋入通道区域的光学装置。 该光学器件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上的与第一导电类型相反的第二导电类型的栅极; 形成在所述半导体衬底下的高密度掺杂剂扩散区，并且掺杂有比所述半导体衬底更高密度的第一导电型掺杂剂; 由半导体材料形成的应变掩埋沟道区域，具有与形成半导体衬底的材料不同的晶格参数，并且在栅极绝缘层和半导体衬底之间延伸以接触高密度掺杂剂扩散区域; 以及形成在栅绝缘层和应变埋入沟道区之间的半导体盖层。
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公开(公告)号：US20090011220A1
公开(公告)日：2009-01-08
申请号：US12153155
申请日：2008-05-14
Applicant: Jung-Hyun Park , Jeong-Woo Park , Sang-Duck Kim , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
Inventor： Jung-Hyun Park , Jeong-Woo Park , Sang-Duck Kim , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
CPC classification number: H05K3/205 , H05K3/108 , H05K3/4602 , H05K2203/1536 , Y10T428/249984 , Y10T428/31504 , Y10T428/31511 , Y10T428/3154 , Y10T428/31678 , Y10T428/31721 , Y10T428/31993
Abstract: A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density.
Abstract translation: 公开了载体和制造印刷电路板的方法。 制造印刷电路板的方法可以包括：在一对剥离层中的每一个上形成第一电路图案，其分别通过粘合剂层附着在基层的任一侧; 将一对释放层从基层分离; 堆叠并将一对释放层压在绝缘基板的任一侧上，使得第一电路图案被埋在绝缘基板中; 并分离一对释放层。 通过利用单一工艺在一对释放层的每一个上形成电路图案，并将电路图案转移到绝缘基板的每一侧，可以缩短制造工艺并且可以以高密度形成电路图案。
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公开(公告)号：US20080310909A1
公开(公告)日：2008-12-18
申请号：US12094978
申请日：2005-12-08
Applicant: Jeong-Woo Park
Inventor： Jeong-Woo Park
IPC: B42F13/20
CPC classification number: B42F13/26
Abstract: A ring binder includes at least two first and second pipes which are hollow inside; a first ring positioned at an end of the first pipe to be opened and closed; a second ring positioned between the first pipe and the second pipe to be opened and closed; a third ring positioned at an end of the second pipe to be opened and closed; and a support bar passing through the first and second pipes and the first through third rings and holding the first and third rings so that the first and third rings are not separated from the first and second pipes, wherein ends of first, second, and third stationary half rings are combined with and separated from ends of first, second, and third rotating half rings.
Abstract translation: 环形活页夹包括至少两个在内部是中空的第一和第二管道; 第一环，其位于所述第一管的端部以被打开和关闭; 位于第一管和第二管之间的第二环，其被打开和关闭; 位于所述第二管的端部以打开和关闭的第三环; 以及支撑杆，其穿过第一和第二管和第一至第三环并保持第一和第三环，使得第一和第三环不与第一和第二管分离，其中第一，第二和第三环的端部 固定半环与第一，第二和第三旋转半环的端部组合并与其分离。
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Patent Agency Ranking
公开(公告)号：US20080101045A1
公开(公告)日：2008-05-01
申请号：US11976070
申请日：2007-10-19
Applicant: Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
Inventor： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。
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17.发明授权Semiconductor integrated circuits including optoelectronic device for changing optical phase 有权包括用于改变光学相位的光电器件的半导体集成电路公开(公告)号：US08422834B2
公开(公告)日：2013-04-16
申请号：US12746167
申请日：2008-06-03
Applicant: Jeong-Woo Park , Gyung-Ock Kim , Mi-Ran Park , Jong-Bum You
Inventor： Jeong-Woo Park , Gyung-Ock Kim , Mi-Ran Park , Jong-Bum You
CPC classification number: G02F1/218 , G02F2001/212 , G02F2201/302
Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit includes a semiconductor pattern disposed on a substrate and including an optical waveguide part and a pair of recessed portions. The optical waveguide part has a thickness ranging from about 0.05 μm to about 0.5 μm. The recessed portions are disposed on both sides of the optical waveguide part and have a thinner thickness than the optical waveguide part. A first doped region and a second doped region are disposed in the recessed portions, respectively. The first and second doped regions are doped with a first conductive type dopant and a second conductive type dopant, respectively. An intrinsic region is formed in at least the optical waveguide part to contact the first and second doped regions.
Abstract translation: 提供了一种半导体集成电路。 半导体集成电路包括设置在基板上并且包括光波导部分和一对凹部的半导体图案。 光波导部分的厚度范围为约0.05μm至约0.5μm。 凹部设置在光波导部分的两侧，并且具有比光波导部分更薄的厚度。 第一掺杂区域和第二掺杂区域分别设置在凹部中。 第一和第二掺杂区域分别掺杂有第一导电型掺杂剂和第二导电型掺杂剂。 在至少光波导部分中形成本征区域以接触第一和第二掺杂区域。
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公开(公告)号：US20120111607A1
公开(公告)日：2012-05-10
申请号：US13354438
申请日：2012-01-20
Applicant: Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
Inventor： Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
IPC: H05K1/02
CPC classification number: H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.
Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。
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公开(公告)号：US08129840B2
公开(公告)日：2012-03-06
申请号：US12503274
申请日：2009-07-15
Applicant: Chajea Jo , Uihyoung Lee , Jae-hyun Phee , Jeong-Woo Park , Ha-Young Yim
Inventor： Chajea Jo , Uihyoung Lee , Jae-hyun Phee , Jeong-Woo Park , Ha-Young Yim
IPC: H01L21/48
CPC classification number: H01L21/563 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L2224/0401 , H01L2224/05558 , H01L2224/06051 , H01L2224/06102 , H01L2224/1146 , H01L2224/11472 , H01L2224/11505 , H01L2224/11902 , H01L2224/11912 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/14104 , H01L2224/1411 , H01L2224/14131 , H01L2224/17107 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.
Abstract translation: 半导体封装以及半导体封装的制造方法。 半导体封装包括基板，其包括多个焊盘和均匀地设置在基板的整个区域上的多个凸块，而与多个焊盘的布置无关。 根据本发明，可以实现工艺的简化，可以降低工艺成本，可以提高可靠性，并且能够容易地进行填充不足。
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公开(公告)号：US07992291B2
公开(公告)日：2011-08-09
申请号：US11976070
申请日：2007-10-19
Applicant: Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
Inventor： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。
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