公开(公告)号：US08418355B2

公开(公告)日：2013-04-16

申请号：US11976071

申请日：2007-10-19

Applicant: Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

Inventor： Sang-Duck Kim ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Jeong-Woo Park

IPC: H05K3/20

CPC classification number: H05K3/20 ,  H05K3/205 ,  H05K3/207 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49163

Abstract: A method for forming transcriptional circuits and a method for manufacturing a circuit board are disclosed. A method of forming a transcriptional circuit, which includes forming an intaglio pattern corresponding to a circuit pattern by selectively forming a resist on a mold board, filling conductive material in the intaglio pattern, and transferring the conductive material onto a carrier by pressing the carrier onto the mold board such that the carrier faces the surface of the mold board having the conductive material filled in, makes it possible to form transcriptional circuits that can be transcribed into an insulation board using existing equipment, whereby costs can be reduced.

Abstract translation: 公开了一种形成转录电路的方法及其制造方法。 一种形成转录电路的方法，其包括通过在模板上选择性地形成抗蚀剂来形成对应于电路图案的凹版图案，将导电材料填充到凹版图案中，以及通过将载体压载到载体上而将载体转移到 使得载体面向具有填充有导电材料的模板的表面的模板，使得可以形成可以使用现有设备转录成绝缘板的转录电路，由此可以降低成本。

公开(公告)号：US20110226626A1

公开(公告)日：2011-09-22

申请号：US13039822

申请日：2011-03-03

Applicant: Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

Inventor： Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

IPC: C25D5/48 ,  H01L21/306

CPC classification number: H01L21/6723 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/6719 ,  H01L21/68728 ,  H01L21/68785

Abstract: A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion.

Abstract translation: 基板处理装置可以包括：电镀处理部，被配置为进行基板的电镀处理;湿处理部，被配置为进行基板的湿式处理;湿处理部位于电镀处理部下;以及基板支撑 被配置为支撑所述基板的部分，使得所述基板的电镀表面面向上，所述基板支撑部分还被配置为在所述电镀处理部分和所述湿处理部分之间移动所述基板。

公开(公告)号：US07972460B2

公开(公告)日：2011-07-05

申请号：US12408366

申请日：2009-03-20

Applicant: Myung-Sam Kang ,  Jung-Hyun Park ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Jung-Hyun Park ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: B32B37/02 ,  H05K1/02 ,  H01L21/70

CPC classification number: B32B38/04 ,  B32B38/10 ,  B32B2038/0092 ,  B32B2038/047 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1064 ,  Y10T156/1082

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom.

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于将一层连接到另一层的通路的印刷电路板的制造方法可以包括在载体的一个表面上形成电路图案; 在载体的一个表面上处理与通孔对应的孔; 将载体的表面压缩到绝缘体的一个表面中; 移除载体; 处理绝缘体上的通孔，对应于孔的位置; 并且在通孔中形成导电材料，从而容易地加工用于形成通孔的孔，并具有高的设计自由度。

公开(公告)号：US07937833B2

公开(公告)日：2011-05-10

申请号：US11976072

申请日：2007-10-19

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H03K3/02

CPC classification number: H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

Abstract translation: 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。

公开(公告)号：US07924492B2

公开(公告)日：2011-04-12

申请号：US12374261

申请日：2007-04-24

Applicant: Hyun-Soo Kim ,  Jeong-Woo Park ,  Bongki Mheen ,  Young-Ahn Leem ,  Gyungock Kim

Inventor： Hyun-Soo Kim ,  Jeong-Woo Park ,  Bongki Mheen ,  Young-Ahn Leem ,  Gyungock Kim

IPC: G02F1/07

CPC classification number: G02F1/025 ,  G02F2203/50 ,  G11C13/04

Abstract: Provided is an optical device having an edge effect with improved phase shift and propagation loss of light without decreasing the dynamic characteristics of the optical device. The optical device includes a first semiconductor layer which is doped with a first type of conductive impurities, and has a recessed groove in an upper portion thereof; a gate insulating layer covering the groove and a portion of the first semiconductor layer; and a second semiconductor layer which covers an upper surface of the gate insulating layer and is doped with a second type of conductive impurities opposite to the first type of conductive impurities.

Abstract translation: 提供一种具有边缘效应的光学器件，具有改善的相移和光的传播损耗，而不会降低光学器件的动态特性。 光学器件包括掺杂有第一类导电杂质的第一半导体层，并且在其上部具有凹槽; 覆盖所述沟槽和所述第一半导体层的一部分的栅极绝缘层; 以及覆盖所述栅极绝缘层的上表面并且掺杂有与所述第一类型的导电杂质相反的第二类导电杂质的第二半导体层。

公开(公告)号：US08633392B2

公开(公告)日：2014-01-21

申请号：US13354438

申请日：2012-01-20

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US08346026B2

公开(公告)日：2013-01-01

申请号：US12517802

申请日：2007-08-07

Applicant: Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

Inventor： Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

IPC: G02F1/035 ,  G02B6/12 ,  G02B6/00

CPC classification number: H01L31/12 ,  H01L27/144

Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.

Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路（IC）。 光电装置包括：基板; 以及在所述衬底上形成为PN二极管的光波导，其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极，其中PN二极管的N型和P型半导体以高浓度掺杂，并且N型半导体的掺杂浓度高于或等于P 型半导体。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC: C25B15/00 ,  C25B9/00

CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

Abstract translation: 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。

公开(公告)号：US07928442B2

公开(公告)日：2011-04-19

申请号：US12441381

申请日：2007-08-17

Applicant: Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

Inventor： Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

IPC: H01L31/036

CPC classification number: G02F1/025 ,  G02F1/2257 ,  H01L33/0037

Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.

Abstract translation: 提供了具有应变埋入通道区域的光学装置。 该光学器件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上的与第一导电类型相反的第二导电类型的栅极; 形成在所述半导体衬底下的高密度掺杂剂扩散区，并且掺杂有比所述半导体衬底更高密度的第一导电型掺杂剂; 由半导体材料形成的应变掩埋沟道区域，具有与形成半导体衬底的材料不同的晶格参数，并且在栅极绝缘层和半导体衬底之间延伸以接触高密度掺杂剂扩散区域; 以及形成在栅绝缘层和应变埋入沟道区之间的半导体盖层。