公开(公告)号：US20050277248A1

公开(公告)日：2005-12-15

申请号：US11107529

申请日：2005-04-15

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Young-Seok Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Jai-Dong Lee ,  Young-Seok Kim ,  Young-Sub You ,  Ki-Su Na ,  Woong Lee

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

摘要翻译： 在制造非易失性半导体存储器的浮置栅极的方法中，在衬底上形成图案以具有露出衬底的一部分的开口。 在图案和基板的暴露部分上形成第一初步多晶硅层以基本上填充开口。 通过部分地蚀刻第一初步多晶硅层直到形成在第一初步多晶硅层中的第一空穴露出来形成第一多晶硅层。 在第一多晶硅层上形成第二多晶硅层。

公开(公告)号：US20050153513A1

公开(公告)日：2005-07-14

申请号：US10992841

申请日：2004-11-22

申请人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Ki-Su Na ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Jai-Dong Lee

发明人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Ki-Su Na ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Jai-Dong Lee

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66825 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/31662 ,  H01L29/40114 ,  H01L29/513

摘要： A method of forming a dielectric layer for a non-volatile memory cell is disclosed. According to the method, a dielectric layer is formed by successively forming a lower oxide layer, a nitride layer and an upper oxide layer on a semiconductor substrate. The lower and upper oxide layers are formed using a radical oxidation process. A method of forming a non-volatile memory cell having the dielectric layer is also disclosed.

摘要翻译： 公开了一种形成用于非易失性存储单元的电介质层的方法。 根据该方法，通过在半导体衬底上依次形成低氧化物层，氮化物层和上部氧化物层来形成电介质层。 使用自由基氧化法形成下层和上层氧化物层。 还公开了一种形成具有电介质层的非易失性存储单元的方法。

公开(公告)号：US5905899A

公开(公告)日：1999-05-18

申请号：US854721

申请日：1997-05-12

申请人： Jung-Hwan Kim ,  Chang-Sub Lee

发明人： Jung-Hwan Kim ,  Chang-Sub Lee

IPC分类号： G06F1/26 ,  G06K15/00 ,  G06F1/32

CPC分类号： G06K15/00 ,  G06F1/266

摘要： A power control device and method capable of performing a power control of the printer in the host computer is provided. A host computer provides a power-on signal to the printer interface, which provides a power-on signal to the power control circuit which delivers DC power to the printer. The power-on signal originates either from a user input at the host computer or the flipping of a soft switch. Similarly, power to the peripheral printer may be disconnected in the same way.

摘要翻译： 提供了一种能够在主计算机中执行打印机的电力控制的电力控制装置和方法。 主计算机向打印机接口提供通电信号，该信号向向打印机传送DC电力的功率控制电路提供通电信号。 电源信号源自主机上的用户输入或软开关的翻转。 类似地，外围打印机的电源可能以相同的方式断开。

公开(公告)号：US09059072B2

公开(公告)日：2015-06-16

申请号：US14294052

申请日：2014-06-02

申请人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

发明人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

IPC分类号： H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L21/683 ,  H01L23/36 ,  H01L23/522 ,  H01L25/18

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

摘要翻译： 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。

公开(公告)号：US08519465B2

公开(公告)日：2013-08-27

申请号：US13553386

申请日：2012-07-19

申请人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

发明人： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US08466527B2

公开(公告)日：2013-06-18

申请号：US12915157

申请日：2010-10-29

申请人： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

发明人： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC分类号： H01L31/0232

CPC分类号： H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

摘要： A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US20120329249A1

公开(公告)日：2012-12-27

申请号：US13530543

申请日：2012-06-22

申请人： Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

发明人： Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

摘要翻译： 提供制造多个半导体芯片的方法。 该方法可以包括在衬底和载体之间提供中间层以将载体与衬底组合，使衬底变薄; 在使衬底变薄之后，将衬底与衬底分离; 在载体与基板分离之后，切割基板以形成多个半导体芯片，其中中间层以第一结合力粘附到载体上，并且中间层以第二结合力粘附到基板 并且其中所述第二结合力大于所述第一结合力。

公开(公告)号：US20110180892A1

公开(公告)日：2011-07-28

申请号：US12915157

申请日：2010-10-29

申请人： Hyung-Sun JANG ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

发明人： Hyung-Sun JANG ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC分类号： H01L31/0232 ,  H01L31/0203

CPC分类号： H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

摘要： A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

摘要翻译： 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US07961180B2

公开(公告)日：2011-06-14

申请号：US11730525

申请日：2007-04-02

申请人： Jung-Hwan Kim

发明人： Jung-Hwan Kim

IPC分类号： G09G5/00

CPC分类号： G02F1/13318 ,  G01J1/46 ,  G09G3/3406 ,  G09G3/3648 ,  G09G2320/0633 ,  G09G2360/145

摘要： An optical sensor providing enhanced reliability in sensing peripheral light and reduced power consumption, and a liquid crystal display device incorporating this optical sensor. In the optical sensor, a first transistor is electrically coupled between a first power supply and a second transistor, which is electrically coupled between the first transistor and a second power supply having a voltage less than that of the first power supply. The first transistor is either turned-on or turned-off according to a control signal. The second transistor controls an amount of an electric current flowing from the first transistor to the second power supply corresponding to an intensity of peripheral light. A sensing section is constructed with a first capacitor electrically coupled to the second transistor in parallel. A gate electrode of the second transistor is electrically coupled to the second power supply.

摘要翻译： 一种提供增强的感测周边光的可靠性和降低的功耗的光学传感器，以及结合该光学传感器的液晶显示装置。 在光学传感器中，第一晶体管电耦合在第一电源和第二晶体管之间，第一晶体管电耦合在第一晶体管和第二电源之间，该第二电源的电压小于第一电源的电压。 第一晶体管根据控制信号被接通或关断。 第二晶体管控制对应于外围光强度的从第一晶体管流向第二电源的电流量。 感测部分构造有并联电耦合到第二晶体管的第一电容器。 第二晶体管的栅电极电耦合到第二电源。

公开(公告)号：US07736963B2

公开(公告)日：2010-06-15

申请号：US11175569

申请日：2005-07-05

申请人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Yong-Woo Hyung ,  Jai-Dong Lee ,  Ki-Su Na ,  Jung-Hwan Kim

发明人： Woong Lee ,  Young-Sub You ,  Hun-Hyeoung Leam ,  Yong-Woo Hyung ,  Jai-Dong Lee ,  Ki-Su Na ,  Jung-Hwan Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28247 ,  H01L27/11568 ,  H01L29/4933

摘要： In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

摘要翻译： 在一个实施例中，形成用于半导体器件的栅极结构的方法包括在半导体衬底上形成初步栅极结构。 预栅极结构包括依次层叠在基板上的栅极氧化物图案和导电图案。 然后，使用包含至少一个氧原子的氧自由基对具有预选择门结构的基板进行再氧化处理，从而在基板的表面和预选择门结构的侧壁上形成氧化物层，形成 半导体器件的栅极结构。 防止栅极氧化物图案的厚度增加，并且提高氧化物层的质量。