公开(公告)号：US09059072B2

公开(公告)日：2015-06-16

申请号：US14294052

申请日：2014-06-02

申请人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

发明人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

IPC分类号： H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L21/683 ,  H01L23/36 ,  H01L23/522 ,  H01L25/18

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

摘要翻译： 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。

公开(公告)号：US08759147B2

公开(公告)日：2014-06-24

申请号：US13235372

申请日：2011-09-17

申请人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

发明人： Eun-Kyoung Choi ,  SeYoung Jeong ,  Kwang-chul Choi ,  Tae Hong Min ,  Chungsun Lee ,  Jung-Hwan Kim

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

摘要翻译： 提供半导体封装及其制造方法。 在一个实施例中，为了制造半导体封装，提供其中制造有半导体芯片的晶片。 在晶片上形成散热层。 散热层接触半导体芯片的顶表面。 此后，从晶片上分离多个半导体芯片。

公开(公告)号：US08791562B2

公开(公告)日：2014-07-29

申请号：US13183645

申请日：2011-07-15

申请人： Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

发明人： Chung-sun Lee ,  Jung-Hwan Kim ,  Yun-hyeok Im ,  Ji-hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-kyoung Choi ,  Tae-hong Min

IPC分类号： H01L23/58 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

摘要翻译： 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US20120329249A1

公开(公告)日：2012-12-27

申请号：US13530543

申请日：2012-06-22

申请人： Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

发明人： Jung-Seok Ahn ,  II Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

摘要翻译： 提供制造多个半导体芯片的方法。 该方法可以包括在衬底和载体之间提供中间层以将载体与衬底组合，使衬底变薄; 在使衬底变薄之后，将衬底与衬底分离; 在载体与基板分离之后，切割基板以形成多个半导体芯片，其中中间层以第一结合力粘附到载体上，并且中间层以第二结合力粘附到基板 并且其中所述第二结合力大于所述第一结合力。

公开(公告)号：US20120018871A1

公开(公告)日：2012-01-26

申请号：US13183645

申请日：2011-07-15

申请人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

发明人： Chung-sun LEE ,  Jung-Hwan Kim ,  Yun-Hyeok Im ,  Ji-Hwan Hwang ,  Hyon-chol Kim ,  Kwang-chul Choi ,  Eun-Kyong Choi ,  Tae-hong Min

IPC分类号： H01L23/58

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

摘要翻译： 可用于三维（3D）系统级封装（SIP））的堆叠封装包括第一半导体芯片，第二半导体芯片和支持器。 第一半导体芯片包括贯通硅通孔（TSV），第二半导体芯片堆叠在第一半导体芯片上，并通过第一半导体芯片的TSV与第一半导体芯片电连接。 支撑件附接到第一半导体芯片上，以便与第二半导体芯片的边缘间隔开。

公开(公告)号：US08890325B2

公开(公告)日：2014-11-18

申请号：US13244544

申请日：2011-09-25

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min

IPC分类号： H01L23/48 ,  H01L33/48 ,  H01L33/62 ,  H01L33/00

CPC分类号： H01L33/486 ,  H01L33/0079 ,  H01L33/62 ,  H01L2224/16 ,  H01L2933/0066

摘要： In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

摘要翻译： 在一个实施例中，异质结结构包括第一衬底; 第二基板，其包括电极焊盘，所述第二基板通过插入在所述第一和第二基板之间的粘合剂层连接到所述第一基板，所述第一基板和所述粘合剂层具有贯穿其中的通孔，以暴露所述电极焊盘的区域; 连接电极，设置在所述通孔中并与所述电极焊盘接触; 以及将连接电极与第一基板电绝缘的绝缘层。 第一和第二基板中的一个具有不同于第一和第二基板中的另一个的热膨胀系数的热膨胀系数，并且粘合剂层或绝缘层中的至少一个包括有机材料。

公开(公告)号：US08450856B2

公开(公告)日：2013-05-28

申请号：US13240533

申请日：2011-09-22

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

公开(公告)号：US20120223433A1

公开(公告)日：2012-09-06

申请号：US13409480

申请日：2012-03-01

申请人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

发明人： Young-kun Jee ,  Ji-hwan Hwang ,  Kwang-chul Choi ,  Jung-hwan Kim ,  Tae-hong Min

IPC分类号： H01L23/488

CPC分类号： B23K35/262 ,  B23K35/3013 ,  B23K35/3033 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

摘要翻译： 一种半导体封装，其包括通过防止形成具有高脆度的金属间化合物而具有可控含量比的能够提高耐久性和可靠性的连接构件。 半导体封装包括基底; 设置在所述基底基板上的第一半导体芯片; 以及第一连接构件，用于电连接基底基板和第一半导体芯片，并且包括第一接合部分，其包括金并且具有被控制以防止AuSn4（Cu，Au）的金属间化合物的金的第一含量比， Sn4或（Ni，Au）Sn4的形成。

公开(公告)号：US20120153498A1

公开(公告)日：2012-06-21

申请号：US13240533

申请日：2011-09-22

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

摘要翻译： 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US09006081B2

公开(公告)日：2015-04-14

申请号：US13530543

申请日：2012-06-22

申请人： Jung-Seok Ahn ,  Il Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

发明人： Jung-Seok Ahn ,  Il Hwan Kim ,  Jung-Hwan Kim ,  Sangwook Park ,  Chungsun Lee ,  Kwang-chul Choi

IPC分类号： H01L21/00 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.

摘要翻译： 提供制造多个半导体芯片的方法。 该方法可以包括在衬底和载体之间提供中间层以将载体与衬底组合，使衬底变薄; 在使衬底变薄之后，将衬底与衬底分离; 在载体与基板分离之后，切割基板以形成多个半导体芯片，其中中间层以第一结合力粘附到载体上，并且中间层以第二结合力粘附到基板 并且其中所述第二结合力大于所述第一结合力。