公开(公告)号：US07005729B2

公开(公告)日：2006-02-28

申请号：US10131168

申请日：2002-04-24

申请人： Yukihiro Murakami ,  Kinya Ichikawa

发明人： Yukihiro Murakami ,  Kinya Ichikawa

IPC分类号： H01L23/495

CPC分类号： H01L25/0657 ,  H01L23/4985 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： In one embodiment of the invention, a die is bonded on a strip carrier frame having a carrier alignment landmark. A tape automated bonding (TAB) strip having a TAB alignment landmark is aligned with the strip carrier frame. The TAB strip is bonded to the strip carrier frame to form a bonded unit.

摘要翻译： 在本发明的一个实施例中，管芯结合在具有载体对准界标的带状载体框架上。 具有TAB对准界标的胶带自动粘合（TAB）条带与带状载体框架对准。 TAB条被粘合到带状载体框架上以形成粘合单元。

公开(公告)号：US06020561A

公开(公告)日：2000-02-01

申请号：US745470

申请日：1996-11-12

申请人： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

发明人： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/12 ,  H05K3/34 ,  H01R9/09

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/14 ,  H05K3/3484 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/114 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K3/1216

摘要： A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

摘要翻译： 一种印刷电路基板，其具有形成在通孔触点和通过通孔触点上的焊料凸块。 印刷电路基板具有至少一个焊盘通孔接触件和至少一个焊盘通过接触件。 第一焊料凸块位于通孔焊盘上，第二焊料凸块位于焊盘通过接触点上。 第一和第二焊料凸块基本上与在与焊接通孔接触件基本上共面的水平面上测量的高度相同。

公开(公告)号：US5660321A

公开(公告)日：1997-08-26

申请号：US623676

申请日：1996-03-29

申请人： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

发明人： Kenzo Ishida ,  Yohko Mashimoto ,  Kinya Ichikawa

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/12 ,  H05K3/34

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/14 ,  H05K3/3484 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/114 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K3/1216

摘要： An method for depositing solder onto the pad-on and pad-off via contacts of a substrate is disclosed. In one embodiment the present invention includes positioning a mask having a first opening of a first diameter and a second opening of a second diameter over a substrate having both pad-on and pad-off via contacts. The substrate is positioned over the substrate such that the first opening is positioned over the pad-on via contact and the second opening is positioned over the pad-off via contact. Solder of a first volume and solder of a second volume are deposited onto the pad-on and pad-off via contacts, respectively, by forcing a solder paste through the mask openings. In this manner, solder bumps having a uniform height and volume above the pad-on via contact plane is established after reflowing the deposited solder.

摘要翻译： 公开了一种通过衬底的触点将焊料沉积到焊盘上和焊盘上的方法。 在一个实施例中，本发明包括将具有第一直径的第一开口和第二直径的第二开口的掩模定位在具有经由接触件的衬垫和衬垫的衬底上。 衬底被定位在衬底上，使得第一开口定位在衬垫穿过接触件上方，并且第二开口通过触点定位在焊盘上方。 第一体积的焊料和第二体积的焊料通过分别通过迫使焊膏通过掩模开口的触点而沉积到焊盘和焊盘上。 以这种方式，在回流沉积的焊料之后建立具有均匀的高度和体积高于焊盘通孔接触面的焊料凸块。

公开(公告)号：US08110920B2

公开(公告)日：2012-02-07

申请号：US12455762

申请日：2009-06-05

申请人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kinya Ichikawa ,  Robert L. Sankman

发明人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kinya Ichikawa ,  Robert L. Sankman

IPC分类号： H01L23/34 ,  H05K1/16

CPC分类号： H01L25/0657 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/82 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01065 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

摘要翻译： 用于处理器的安装基板包括裸片侧和在裸片侧配置有处理器占位面的平台侧。 处理器占用面积耦合到至少一个处理器互连，并且微电子管芯嵌入在安装衬底中。 微电子管芯耦合到处理器互连，并且待处理器占用的处理器之间的通信速率在10Gb / s至1Tb / s之间。

公开(公告)号：US07132739B2

公开(公告)日：2006-11-07

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L23/31

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US07097462B2

公开(公告)日：2006-08-29

申请号：US10881243

申请日：2004-06-29

申请人： Kinya Ichikawa

发明人： Kinya Ichikawa

IPC分类号： H01R12/00

CPC分类号： H05K3/3436 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01R12/714 ,  H05K1/141 ,  H05K3/305 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

摘要： Embodiments include a generally planar patch substrate having external connection pads on one side, electrical connections connected to the external connection pads and extending through the substrate, and plated contacts formed on the electrical connections and extending beyond the other side of the patch substrate. The external connection pads may be connected to one electrical device using solder bumps or balls, and the plated contacts may be connected to contacts of another electrical device by thermo-compression bonding. Also, a surface of the patch substrate having the plated contacts may be attached to the other electrical device using an electrically insulating adhesive. Moreover, the plated contacts may have a smaller surface area than the external connection pads, so that the other electrical device can also have smaller contacts, leaving more space for electrically conductive traces to the contacts on the surface and within layers of the other electrical device.

公开(公告)号：US20050085034A1

公开(公告)日：2005-04-21

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065 ,  H01L29/74

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US5811883A

公开(公告)日：1998-09-22

申请号：US724175

申请日：1996-09-30

申请人： Kinya Ichikawa ,  Seiichiroh Seki ,  Takaya Miwa ,  Yohko Mashimoto

发明人： Kinya Ichikawa ,  Seiichiroh Seki ,  Takaya Miwa ,  Yohko Mashimoto

IPC分类号： H01L23/13 ,  H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K3/18 ,  H05K3/34 ,  H05K3/46 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3452 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0266 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2201/09936 ,  H05K2203/0574 ,  H05K3/184 ,  H05K3/4602

摘要： A substrate for an integrated circuit package is provided. The substrate includes a first dielectric layer with a first coefficient of thermal expansion. The first dielectric layer has a bottom surface and an inner side surface. The inner side surface defines a first aperture. The substrate also includes a conductive pad having a bottom surface and a side surface. The side surface of the conductive pad engages the inner side surface of the first dielectric layer. The substrate further includes a second dielectric layer having a second coefficient of thermal expansion closely matching the first coefficient of thermal expansion. The second dielectric layer is deposited upon the bottom surface of the first dielectric layer and upon a first portion of the bottom surface of the conductive pad. The first portion of the bottom surface of the conductive pad is adjacent to the side surface of the conductive pad.

摘要翻译： 提供了一种集成电路封装的基板。 衬底包括具有第一热膨胀系数的第一介电层。 第一电介质层具有底表面和内侧表面。 内侧表面限定第一孔。 衬底还包括具有底表面和侧表面的导电焊盘。 导电垫的侧表面与第一介电层的内侧表面接合。 衬底还包括具有与第一热膨胀系数近似匹配的第二热膨胀系数的第二电介质层。 第二电介质层沉积在第一电介质层的底表面上并且沉积在导电焊盘的底表面的第一部分上。 导电垫的底表面的第一部分与导电垫的侧表面相邻。

公开(公告)号：US20150084210A1

公开(公告)日：2015-03-26

申请号：US14036719

申请日：2013-09-25

申请人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

发明人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

IPC分类号： H01L23/00

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15747 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2203/013 ,  H01L2924/00014 ,  H01L2924/00

摘要： Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

摘要翻译： 这里通常讨论的是包括密集互连桥和其制造技术的系统和装置。 根据一个示例，一种技术可以包括创建多芯基板，在多芯基板上印刷互连桥，通过将第一和第二裸片耦合通过互连桥将第一裸片电耦合到第二裸片。

公开(公告)号：US20120112336A1

公开(公告)日：2012-05-10

申请号：US12940446

申请日：2010-11-05

申请人： John S. Guzek ,  Robert L. Sankman ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Jiro Kubota

发明人： John S. Guzek ,  Robert L. Sankman ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Jiro Kubota

IPC分类号： H01L23/528 ,  H01L21/48

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

摘要： An encapsulated die (100, 401) comprises a substrate (110, 510) having a first surface (111), an opposing second surface (112), and intervening side surfaces (113), with active devices located at the first surface of the substrate. The active devices are connected by a plurality of electrically conductive layers (120, 520) that are separated from each other by a plurality of electrically insulating layers (125, 525). A protective cap (130, 530) is located over the first surface of the substrate contains an interconnect structure (140) exposed at a surface (131) thereof. In another embodiment, a microelectronic package (200) comprises a package substrate (250) with an encapsulated die (100) such as was described above embedded therein.

摘要翻译： 封装的管芯（100,401）包括具有第一表面（111），相对的第二表面（112）和中间的侧表面（113）的衬底（110,510），其中有源器件位于第一表面 基质。 有源器件通过由多个电绝缘层（125,525）彼此分离的多个导电层（120,520）连接。 保护盖（130,530）位于衬底的第一表面之上，包含暴露在其表面（131）处的互连结构（140）。 在另一个实施例中，微电子封装（200）包括具有如上所述的封装管芯（100）的封装衬底（250）。